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ea4584d73d
This code performs DDR3 memory calibration for display5 board. Signed-off-by: Lukasz Majewski <lukma@denx.de>
322 lines
7.6 KiB
C
322 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include "asm/arch/crm_regs.h"
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/imx-regs.h>
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#include "asm/arch/iomux.h"
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/gpio.h>
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#include <environment.h>
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#include <fsl_esdhc.h>
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#include <netdev.h>
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#include <bootcount.h>
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#include <watchdog.h>
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_dqm2 = 0x00000030,
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.dram_dqm3 = 0x00000030,
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.dram_dqm4 = 0x00000030,
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.dram_dqm5 = 0x00000030,
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.dram_dqm6 = 0x00000030,
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.dram_dqm7 = 0x00000030,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* 4x128Mx16.cfg */
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static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
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.p0_mpwldectrl0 = 0x002D0028,
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.p0_mpwldectrl1 = 0x0032002D,
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.p1_mpwldectrl0 = 0x00210036,
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.p1_mpwldectrl1 = 0x0019002E,
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.p0_mpdgctrl0 = 0x4349035C,
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.p0_mpdgctrl1 = 0x0348033D,
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.p1_mpdgctrl0 = 0x43550362,
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.p1_mpdgctrl1 = 0x03520316,
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.p0_mprddlctl = 0x41393940,
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.p1_mprddlctl = 0x3F3A3C47,
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.p0_mpwrdlctl = 0x413A423A,
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.p1_mpwrdlctl = 0x4042483E,
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};
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/* MT41K128M16JT-125 (2Gb density) */
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static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC3F, &ccm->CCGR1);
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writel(0x0FFFCFC0, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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#ifdef CONFIG_MX6_DDRCAL
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static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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struct mx6_mmdc_calibration calibration = {0};
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mmdc_read_calibration(sysinfo, &calibration);
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debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
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debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
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debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
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debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
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debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
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debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
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debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
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debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
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debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
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debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
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debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
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debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
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}
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static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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int ret;
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/* Perform DDR DRAM calibration */
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udelay(100);
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ret = mmdc_do_write_level_calibration(sysinfo);
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if (ret) {
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printf("DDR: Write level calibration error [%d]\n", ret);
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return;
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}
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ret = mmdc_do_dqs_calibration(sysinfo);
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if (ret) {
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printf("DDR: DQS calibration error [%d]\n", ret);
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return;
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}
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spl_dram_print_cal(sysinfo);
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}
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#endif /* CONFIG_MX6_DDRCAL */
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.pd_fast_exit = 1, /* enable precharge power-down fast exit */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
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#ifdef CONFIG_MX6_DDRCAL
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spl_dram_perform_cal(&sysinfo);
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#endif
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}
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#ifdef CONFIG_SPL_SPI_SUPPORT
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static void displ5_init_ecspi(void)
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{
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displ5_set_iomux_ecspi_spl();
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enable_spi_clk(1, 1);
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}
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#else
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static inline void displ5_init_ecspi(void) { }
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#endif
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#ifdef CONFIG_SPL_MMC_SUPPORT
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static struct fsl_esdhc_cfg usdhc_cfg = {
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.esdhc_base = USDHC4_BASE_ADDR,
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.max_bus_width = 8,
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};
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int board_mmc_init(bd_t *bd)
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{
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displ5_set_iomux_usdhc_spl();
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
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return fsl_esdhc_initialize(bd, &usdhc_cfg);
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}
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#endif
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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arch_cpu_init();
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gpr_init();
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/* setup GP timer */
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timer_init();
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displ5_set_iomux_uart_spl();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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displ5_init_ecspi();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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displ5_set_iomux_misc_spl();
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/* Initialize and reset WDT in SPL */
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hw_watchdog_init();
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WATCHDOG_RESET();
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#define EM_PAD IMX_GPIO_NR(3, 29)
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int board_check_emergency_pad(void)
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{
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int ret;
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ret = gpio_direction_input(EM_PAD);
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if (ret)
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return ret;
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return !gpio_get_value(EM_PAD);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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/* Default boot sequence SPI -> MMC */
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spl_boot_list[0] = spl_boot_device();
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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spl_boot_list[2] = BOOT_DEVICE_UART;
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spl_boot_list[3] = BOOT_DEVICE_NONE;
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/*
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* In case of emergency PAD pressed, we always boot
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* to proper u-boot and perform recovery tasks there.
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*/
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if (board_check_emergency_pad())
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return;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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/* 'fastboot' */
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const char *s;
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if (env_init() || env_load())
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return;
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s = env_get("BOOT_FROM");
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if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
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spl_boot_list[0] = BOOT_DEVICE_MMC1;
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spl_boot_list[1] = spl_boot_device();
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}
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#endif
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}
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void reset_cpu(ulong addr) {}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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if (env_get_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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