mirror of
https://xff.cz/git/u-boot/
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8a65bd6372
Rename fb_set_reboot_flag to fastboot_set_reboot_flag so it matches all other fastboot code in the global name space. Fix the guards around them so that they're dependent on FASTBOOT, not just USB_FUNCTION_FASTBOOT. Move the weak implementation of fastboot_set_reboot_flag to fb_common.c so we can call it from non-USB fastboot code. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
155 lines
3.3 KiB
C
155 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/grf_rk322x.h>
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#include <asm/arch/boot_mode.h>
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DECLARE_GLOBAL_DATA_PTR;
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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setup_boot_mode();
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return rk_board_late_init();
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}
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int board_init(void)
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{
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#include <asm/arch/grf_rk322x.h>
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/* Enable early UART2 channel 1 on the RK322x */
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#define GRF_BASE 0x11000000
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struct rk322x_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_GPIO = 0,
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GPIO1B2_UART21_SIN,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART1_SOUT,
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GPIO1B1_UART21_SOUT,
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};
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enum {
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CON_IOMUX_UART2SEL_SHIFT= 8,
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CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
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CON_IOMUX_UART2SEL_2 = 0,
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CON_IOMUX_UART2SEL_21,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
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GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->con_iomux,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
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/*
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* The integrated macphy is enabled by default, disable it
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* for saving power consuming.
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*/
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rk_clrsetreg(&grf->macphy_con[0],
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MACPHY_CFG_ENABLE_MASK,
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0 << MACPHY_CFG_ENABLE_SHIFT);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = 0x8400000;
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/* Reserve 0x200000 for OPTEE */
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gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
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+ gd->bd->bi_dram[0].size + 0x200000;
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gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
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+ gd->ram_size - gd->bd->bi_dram[1].start;
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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static struct dwc2_plat_otg_data rk322x_otg_data = {
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.rx_fifo_sz = 512,
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.np_tx_fifo_sz = 16,
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.tx_fifo_sz = 128,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node;
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const char *mode;
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bool matched = false;
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const void *blob = gd->fdt_blob;
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/* find the usb_otg node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3288-usb");
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while (node > 0) {
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mode = fdt_getprop(blob, node, "dr_mode", NULL);
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if (mode && strcmp(mode, "otg") == 0) {
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matched = true;
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break;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"rockchip,rk3288-usb");
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}
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if (!matched) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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return dwc2_udc_probe(&rk322x_otg_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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#endif
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#if CONFIG_IS_ENABLED(FASTBOOT)
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int fastboot_set_reboot_flag(void)
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{
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struct rk322x_grf *grf;
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printf("Setting reboot to fastboot flag ...\n");
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/* Set boot mode to fastboot */
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writel(BOOT_FASTBOOT, &grf->os_reg[0]);
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return 0;
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}
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#endif
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