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	The ti816x SoC revision of the ethernet IP block is handled by the "davinci_emac" driver, rather than the "cpsw" driver as done by later members of the family. Enable the relevant plumbing. Signed-off-by: Sriramakrishnan <srk@ti.com> Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			63 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			63 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * hardware_ti816x.h
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|  *
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|  * TI816x hardware specific header
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|  *
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|  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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|  * Antoine Tenart, <atenart@adeneo-embedded.com>
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|  * Based on TI-PSP-04.00.02.14
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  */
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| 
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| #ifndef __AM33XX_HARDWARE_TI816X_H
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| #define __AM33XX_HARDWARE_TI816X_H
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| 
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| /* UART */
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| #define UART0_BASE		0x48020000
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| #define UART1_BASE		0x48022000
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| #define UART2_BASE		0x48024000
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| 
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| /* Watchdog Timer */
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| #define WDT_BASE		0x480C2000
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| 
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| /* Control Module Base Address */
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| #define CTRL_BASE		0x48140000
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| #define CTRL_DEVICE_BASE	0x48140600
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| 
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| /* PRCM Base Address */
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| #define PRCM_BASE		0x48180000
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| 
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| #define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
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| #define PRM_RSTST		(PRM_RSTCTRL + 8)
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| 
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| /* VTP Base address */
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| #define VTP0_CTRL_ADDR		0x48198358
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| #define VTP1_CTRL_ADDR		0x4819A358
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| 
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| /* DDR Base address */
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| #define DDR_PHY_CMD_ADDR	0x48198000
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| #define DDR_PHY_DATA_ADDR	0x481980C8
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| #define DDR_PHY_CMD_ADDR2	0x4819A000
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| #define DDR_PHY_DATA_ADDR2	0x4819A0C8
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| #define DDR_DATA_REGS_NR	4
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| 
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| 
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| #define DDRPHY_0_CONFIG_BASE	0x48198000
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| #define DDRPHY_1_CONFIG_BASE	0x4819A000
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| #define DDRPHY_CONFIG_BASE	((emif == 0) ? \
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| 	DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
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| 
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| /* RTC base address */
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| #define RTC_BASE		0x480C0000
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| 
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| #endif /* __AM33XX_HARDWARE_TI816X_H */
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