York Sun 6c6e006a20 driver/ddr/fsl: Update timing config for heavy load ...

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>

2015-12-13 18:27:27 -08:00

..

arm_ddr_gen3.c

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ctrl_regs.c

driver/ddr/fsl: Update timing config for heavy load

2015-12-13 18:27:27 -08:00

ddr1_dimm_params.c

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ddr2_dimm_params.c

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ddr3_dimm_params.c

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ddr4_dimm_params.c

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fsl_ddr_gen4.c

driver/ddr/fsl: Update workaround for A008511 for vref range

2015-12-13 18:27:27 -08:00

interactive.c

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lc_common_dimm_params.c

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main.c

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

2015-11-30 09:11:11 -08:00

Makefile

Various Makefiles: Add SPDX-License-Identifier tags

2015-11-10 09:19:52 -05:00

mpc85xx_ddr_gen1.c

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mpc85xx_ddr_gen2.c

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mpc85xx_ddr_gen3.c

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mpc86xx_ddr.c

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options.c

driver/ddr/fsl: Update DDR4 RTT values

2015-12-13 18:27:27 -08:00

util.c

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

2015-11-30 09:11:11 -08:00