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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K2HK: SoC definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2HK_H
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#define __ASM_ARCH_HARDWARE_K2HK_H
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#define KS2_ARM_PLL_EN BIT(13)
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x02000000
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_MOD 0
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#define KS2_LPSC_DUMMY1 1
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#define KS2_LPSC_USB 2
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#define KS2_LPSC_EMIF25_SPI 3
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#define KS2_LPSC_TSIP 4
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#define KS2_LPSC_DEBUGSS_TRC 5
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#define KS2_LPSC_TETB_TRC 6
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#define KS2_LPSC_PKTPROC 7
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#define KS2_LPSC_PA KS2_LPSC_PKTPROC
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#define KS2_LPSC_SGMII 8
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#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
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#define KS2_LPSC_CRYPTO 9
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#define KS2_LPSC_PCIE 10
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#define KS2_LPSC_SRIO 11
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#define KS2_LPSC_VUSR0 12
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#define KS2_LPSC_CHIP_SRSS 13
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#define KS2_LPSC_MSMC 14
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#define KS2_LPSC_GEM_1 16
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#define KS2_LPSC_GEM_2 17
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#define KS2_LPSC_GEM_3 18
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#define KS2_LPSC_GEM_4 19
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#define KS2_LPSC_GEM_5 20
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#define KS2_LPSC_GEM_6 21
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#define KS2_LPSC_GEM_7 22
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#define KS2_LPSC_EMIF4F_DDR3A 23
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#define KS2_LPSC_EMIF4F_DDR3B 24
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#define KS2_LPSC_TAC 25
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#define KS2_LPSC_RAC 26
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#define KS2_LPSC_RAC_1 27
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#define KS2_LPSC_FFTC_A 28
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#define KS2_LPSC_FFTC_B 29
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#define KS2_LPSC_FFTC_C 30
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#define KS2_LPSC_FFTC_D 31
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#define KS2_LPSC_FFTC_E 32
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#define KS2_LPSC_FFTC_F 33
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#define KS2_LPSC_AI2 34
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#define KS2_LPSC_TCP3D_0 35
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#define KS2_LPSC_TCP3D_1 36
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#define KS2_LPSC_TCP3D_2 37
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#define KS2_LPSC_TCP3D_3 38
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#define KS2_LPSC_VCP2X4_A 39
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#define KS2_LPSC_CP2X4_B 40
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#define KS2_LPSC_VCP2X4_C 41
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#define KS2_LPSC_VCP2X4_D 42
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#define KS2_LPSC_VCP2X4_E 43
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#define KS2_LPSC_VCP2X4_F 44
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#define KS2_LPSC_VCP2X4_G 45
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#define KS2_LPSC_VCP2X4_H 46
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#define KS2_LPSC_BCP 47
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#define KS2_LPSC_DXB 48
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#define KS2_LPSC_VUSR1 49
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#define KS2_LPSC_XGE 50
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#define KS2_LPSC_ARM_SREFLEX 51
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/* DDR3B definitions */
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#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
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#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
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#define KS2_DDR3B_DDRPHYC 0x02328000
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
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channel 29 */
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/* SGMII SerDes */
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#define KS2_LANES_PER_SGMII_SERDES 4
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 8
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/* NETCP pktdma */
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#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
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#define KS2_NETCP_PDMA_TX_BASE 0x02004400
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#define KS2_NETCP_PDMA_TX_CH_NUM 9
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#define KS2_NETCP_PDMA_RX_BASE 0x02004800
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#define KS2_NETCP_PDMA_RX_CH_NUM 26
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#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
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#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
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#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
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#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
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/* NETCP */
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#define KS2_NETCP_BASE 0x02000000
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#endif /* __ASM_ARCH_HARDWARE_H */
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