Vignesh Raghavendra 7262ff7e56 ARM: dts: k3-j721s2: Correct timer frequency ...

MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.

Without this delays in R5 SPL are 10x off.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

2022-04-11 11:39:19 -04:00

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arc

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arm

ARM: dts: k3-j721s2: Correct timer frequency

2022-04-11 11:39:19 -04:00

m68k

Convert CONFIG_MCFRTC et al to Kconfig

2022-04-01 10:28:46 -04:00

microblaze

microblaze: Migrate DCACHE/ICACHE to Kconfig

2022-04-08 10:46:22 -04:00

mips

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nds32

nds32: Migrate CONFIG_DEBUG_LED to Kconfig

2022-04-08 10:46:22 -04:00

nios2

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powerpc

powerpc: mpc83xx: Migrate DEFAULT_IMMR to Kconfig

2022-04-08 10:46:22 -04:00

riscv

riscv: alloc space exhausted

2022-04-06 10:58:13 +08:00

sandbox

arch: Kconfig: imply BINMAN for SANDBOX

2022-03-31 14:12:01 -04:00

sh

Split CONFIG_CC_OPTIMIZE_FOR_SIZE into two configs

2022-03-25 13:35:50 -04:00

x86

Merge branch 'next'

2022-04-04 10:48:44 -04:00

xtensa

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.gitignore

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Kconfig

Merge branch 'next'

2022-04-04 10:48:44 -04:00

u-boot-elf.lds

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