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cd52c3253a
Add clock driver for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> [trini: Redo whitespace] Signed-off-by: Tom Rini <trini@konsulko.com>
252 lines
6.7 KiB
C
252 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 BayLibre, SAS
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT8516_H
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#define _DT_BINDINGS_CLK_MT8516_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_APLL1 4
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#define CLK_APMIXED_APLL2 5
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#define CLK_APMIXED_NR_CLK 6
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/* TOPCKGEN */
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#define CLK_TOP_CLK_NULL 0
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#define CLK_TOP_I2S_INFRA_BCK 1
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#define CLK_TOP_MEMPLL 2
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#define CLK_TOP_DMPLL 3
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#define CLK_TOP_MAINPLL_D2 4
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#define CLK_TOP_MAINPLL_D4 5
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#define CLK_TOP_MAINPLL_D8 6
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#define CLK_TOP_MAINPLL_D16 7
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#define CLK_TOP_MAINPLL_D11 8
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#define CLK_TOP_MAINPLL_D22 9
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#define CLK_TOP_MAINPLL_D3 10
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#define CLK_TOP_MAINPLL_D6 11
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#define CLK_TOP_MAINPLL_D12 12
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#define CLK_TOP_MAINPLL_D5 13
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#define CLK_TOP_MAINPLL_D10 14
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#define CLK_TOP_MAINPLL_D20 15
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#define CLK_TOP_MAINPLL_D40 16
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#define CLK_TOP_MAINPLL_D7 17
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#define CLK_TOP_MAINPLL_D14 18
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#define CLK_TOP_UNIVPLL_D2 19
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#define CLK_TOP_UNIVPLL_D4 20
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#define CLK_TOP_UNIVPLL_D8 21
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#define CLK_TOP_UNIVPLL_D16 22
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#define CLK_TOP_UNIVPLL_D3 23
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#define CLK_TOP_UNIVPLL_D6 24
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#define CLK_TOP_UNIVPLL_D12 25
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#define CLK_TOP_UNIVPLL_D24 26
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#define CLK_TOP_UNIVPLL_D5 27
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#define CLK_TOP_UNIVPLL_D20 28
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#define CLK_TOP_MMPLL380M 29
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#define CLK_TOP_MMPLL_D2 30
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#define CLK_TOP_MMPLL_200M 31
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#define CLK_TOP_USB_PHY48M 32
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#define CLK_TOP_APLL1 33
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#define CLK_TOP_APLL1_D2 34
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#define CLK_TOP_APLL1_D4 35
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#define CLK_TOP_APLL1_D8 36
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#define CLK_TOP_APLL2 37
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#define CLK_TOP_APLL2_D2 38
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#define CLK_TOP_APLL2_D4 39
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#define CLK_TOP_APLL2_D8 40
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#define CLK_TOP_CLK26M 41
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#define CLK_TOP_CLK26M_D2 42
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#define CLK_TOP_AHB_INFRA_D2 43
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#define CLK_TOP_NFI1X 44
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#define CLK_TOP_ETH_D2 45
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#define CLK_TOP_UART0_SEL 46
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#define CLK_TOP_GFMUX_EMI1X_SEL 47
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#define CLK_TOP_EMI_DDRPHY_SEL 48
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#define CLK_TOP_AHB_INFRA_SEL 49
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#define CLK_TOP_CSW_MUX_MFG_SEL 50
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#define CLK_TOP_MSDC0_SEL 51
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#define CLK_TOP_PWM_MM_SEL 52
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#define CLK_TOP_UART1_SEL 53
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#define CLK_TOP_MSDC1_SEL 54
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#define CLK_TOP_SPM_52M_SEL 55
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#define CLK_TOP_PMICSPI_SEL 56
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#define CLK_TOP_QAXI_AUD26M_SEL 57
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#define CLK_TOP_AUD_INTBUS_SEL 58
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#define CLK_TOP_NFI2X_PAD_SEL 59
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#define CLK_TOP_NFI1X_PAD_SEL 60
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#define CLK_TOP_MFG_MM_SEL 61
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#define CLK_TOP_DDRPHYCFG_SEL 62
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#define CLK_TOP_USB_78M_SEL 63
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#define CLK_TOP_SPINOR_SEL 64
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#define CLK_TOP_MSDC2_SEL 65
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#define CLK_TOP_ETH_SEL 66
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#define CLK_TOP_AXI_MFG_IN_SEL 67
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#define CLK_TOP_SLOW_MFG_SEL 68
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#define CLK_TOP_AUD1_SEL 69
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#define CLK_TOP_AUD2_SEL 70
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#define CLK_TOP_AUD_ENGEN1_SEL 71
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#define CLK_TOP_AUD_ENGEN2_SEL 72
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#define CLK_TOP_I2C_SEL 73
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#define CLK_TOP_AUD_I2S0_M_SEL 74
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#define CLK_TOP_AUD_I2S1_M_SEL 75
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#define CLK_TOP_AUD_I2S2_M_SEL 76
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#define CLK_TOP_AUD_I2S3_M_SEL 77
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#define CLK_TOP_AUD_I2S4_M_SEL 78
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#define CLK_TOP_AUD_I2S5_M_SEL 79
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#define CLK_TOP_AUD_SPDIF_B_SEL 80
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#define CLK_TOP_PWM_SEL 81
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#define CLK_TOP_SPI_SEL 82
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#define CLK_TOP_AUD_SPDIFIN_SEL 83
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#define CLK_TOP_UART2_SEL 84
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#define CLK_TOP_BSI_SEL 85
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#define CLK_TOP_DBG_ATCLK_SEL 86
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#define CLK_TOP_CSW_NFIECC_SEL 87
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#define CLK_TOP_NFIECC_SEL 88
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#define CLK_TOP_APLL12_CK_DIV0 89
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#define CLK_TOP_APLL12_CK_DIV1 90
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#define CLK_TOP_APLL12_CK_DIV2 91
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#define CLK_TOP_APLL12_CK_DIV3 92
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#define CLK_TOP_APLL12_CK_DIV4 93
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#define CLK_TOP_APLL12_CK_DIV4B 94
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#define CLK_TOP_APLL12_CK_DIV5 95
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#define CLK_TOP_APLL12_CK_DIV5B 96
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#define CLK_TOP_APLL12_CK_DIV6 97
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#define CLK_TOP_NR_CLK 98
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/* TOPCKGEN Gates */
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#define CLK_TOP_PWM_MM 0
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#define CLK_TOP_MFG_MM 1
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#define CLK_TOP_SPM_52M 2
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#define CLK_TOP_THEM 3
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#define CLK_TOP_APDMA 4
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#define CLK_TOP_I2C0 5
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#define CLK_TOP_I2C1 6
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#define CLK_TOP_AUXADC1 7
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#define CLK_TOP_NFI 8
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#define CLK_TOP_NFIECC 9
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#define CLK_TOP_DEBUGSYS 10
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#define CLK_TOP_PWM 11
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#define CLK_TOP_UART0 12
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#define CLK_TOP_UART1 13
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#define CLK_TOP_BTIF 14
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#define CLK_TOP_USB 15
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#define CLK_TOP_FLASHIF_26M 16
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#define CLK_TOP_AUXADC2 17
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#define CLK_TOP_I2C2 18
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#define CLK_TOP_MSDC0 19
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#define CLK_TOP_MSDC1 20
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#define CLK_TOP_NFI2X 21
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#define CLK_TOP_PMICWRAP_AP 22
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#define CLK_TOP_SEJ 23
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#define CLK_TOP_MEMSLP_DLYER 24
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#define CLK_TOP_SPI 25
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#define CLK_TOP_APXGPT 26
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#define CLK_TOP_AUDIO 27
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#define CLK_TOP_PMICWRAP_MD 28
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#define CLK_TOP_PMICWRAP_CONN 29
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#define CLK_TOP_PMICWRAP_26M 30
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#define CLK_TOP_AUX_ADC 31
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#define CLK_TOP_AUX_TP 32
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#define CLK_TOP_MSDC2 33
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#define CLK_TOP_RBIST 34
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#define CLK_TOP_NFI_BUS 35
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#define CLK_TOP_GCE 36
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#define CLK_TOP_TRNG 37
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#define CLK_TOP_SEJ_13M 38
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#define CLK_TOP_AES 39
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#define CLK_TOP_PWM_B 40
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#define CLK_TOP_PWM1_FB 41
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#define CLK_TOP_PWM2_FB 42
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#define CLK_TOP_PWM3_FB 43
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#define CLK_TOP_PWM4_FB 44
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#define CLK_TOP_PWM5_FB 45
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#define CLK_TOP_USB_1P 46
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#define CLK_TOP_FLASHIF_FREERUN 47
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#define CLK_TOP_66M_ETH 48
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#define CLK_TOP_133M_ETH 49
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#define CLK_TOP_FETH_25M 50
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#define CLK_TOP_FETH_50M 51
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#define CLK_TOP_FLASHIF_AXI 52
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#define CLK_TOP_USBIF 53
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#define CLK_TOP_UART2 54
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#define CLK_TOP_BSI 55
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#define CLK_TOP_MSDC0_INFRA 56
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#define CLK_TOP_MSDC1_INFRA 57
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#define CLK_TOP_MSDC2_INFRA 58
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#define CLK_TOP_USB_78M 59
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#define CLK_TOP_RG_SPINOR 60
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#define CLK_TOP_RG_MSDC2 61
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#define CLK_TOP_RG_ETH 62
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#define CLK_TOP_RG_AXI_MFG 63
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#define CLK_TOP_RG_SLOW_MFG 64
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#define CLK_TOP_RG_AUD1 65
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#define CLK_TOP_RG_AUD2 66
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#define CLK_TOP_RG_AUD_ENGEN1 67
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#define CLK_TOP_RG_AUD_ENGEN2 68
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#define CLK_TOP_RG_I2C 69
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#define CLK_TOP_RG_PWM_INFRA 70
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#define CLK_TOP_RG_AUD_SPDIF_IN 71
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#define CLK_TOP_RG_UART2 72
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#define CLK_TOP_RG_BSI 73
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#define CLK_TOP_RG_DBG_ATCLK 74
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#define CLK_TOP_RG_NFIECC 75
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#define CLK_TOP_RG_APLL1_D2_EN 76
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#define CLK_TOP_RG_APLL1_D4_EN 77
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#define CLK_TOP_RG_APLL1_D8_EN 78
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#define CLK_TOP_RG_APLL2_D2_EN 79
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#define CLK_TOP_RG_APLL2_D4_EN 80
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#define CLK_TOP_RG_APLL2_D8_EN 81
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#define CLK_TOP_APLL12_DIV0 82
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#define CLK_TOP_APLL12_DIV1 83
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#define CLK_TOP_APLL12_DIV2 84
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#define CLK_TOP_APLL12_DIV3 85
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#define CLK_TOP_APLL12_DIV4 86
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#define CLK_TOP_APLL12_DIV4B 87
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#define CLK_TOP_APLL12_DIV5 88
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#define CLK_TOP_APLL12_DIV5B 89
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#define CLK_TOP_APLL12_DIV6 90
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/* INFRACFG */
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#define CLK_IFR_MUX1_SEL 0
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#define CLK_IFR_ETH_25M_SEL 1
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#define CLK_IFR_I2C0_SEL 2
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#define CLK_IFR_I2C1_SEL 3
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#define CLK_IFR_I2C2_SEL 4
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#define CLK_IFR_NR_CLK 5
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/* AUDIOTOP */
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#define CLK_AUD_AFE 0
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#define CLK_AUD_I2S 1
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#define CLK_AUD_22M 2
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#define CLK_AUD_24M 3
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#define CLK_AUD_INTDIR 4
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#define CLK_AUD_APLL2_TUNER 5
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#define CLK_AUD_APLL_TUNER 6
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#define CLK_AUD_HDMI 7
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#define CLK_AUD_SPDF 8
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#define CLK_AUD_ADC 9
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#define CLK_AUD_DAC 10
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#define CLK_AUD_DAC_PREDIS 11
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#define CLK_AUD_TML 12
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#define CLK_AUD_NR_CLK 13
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/* MFGCFG */
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#define CLK_MFG_BAXI 0
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#define CLK_MFG_BMEM 1
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#define CLK_MFG_BG3D 2
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#define CLK_MFG_B26M 3
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#define CLK_MFG_NR_CLK 4
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#endif /* _DT_BINDINGS_CLK_MT8516_H */
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