Paweł Anikiel 5c53d9c0d9 socfpga: arria10: Wait for fifo empty after writing bitstream ...

For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

2022-07-01 14:57:14 +08:00

..

ACEX1K.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

altera.c

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09 17:53:12 +08:00

cyclon2.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

fpga.c

common: Drop log.h from common header

2020-05-18 21:19:18 -04:00

intel_sdm_mb.c

arm: socfpga: soc64: Add ATF support for FPGA reconfig driver

2021-01-15 17:48:37 +08:00

ivm_core.c

common: Drop log.h from common header

2020-05-18 21:19:18 -04:00

Kconfig

arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64

2021-03-08 10:59:10 +08:00

lattice.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

Makefile

fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

2020-10-09 17:53:12 +08:00

socfpga_arria10.c

socfpga: arria10: Wait for fifo empty after writing bitstream

2022-07-01 14:57:14 +08:00

socfpga_gen5.c

arm: socfpga: Convert system manager from struct to defines

2020-01-07 14:38:33 +01:00

socfpga.c

WS cleanup: remove trailing empty lines

2021-09-30 08:08:56 -04:00

spartan2.c

…

spartan3.c

…

stratixII.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

stratixv.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

versalpl.c

xilinx: zynqmp: synchronize firmware call return payload

2020-08-20 09:49:20 +02:00

virtex2.c

common: Drop linux/delay.h from common header

2020-05-18 21:19:23 -04:00

xilinx.c

common: Drop log.h from common header

2020-05-18 21:19:18 -04:00

zynqmppl.c

common: Drop asm/global_data.h from common header

2021-02-02 15:33:42 -05:00

zynqpl.c

fpga: zynqpl: fix buffer alignment

2021-02-23 14:56:55 +01:00