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The glitch in the SPI clock line, which commit3cea335c34
(spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commitd36b39bf0d
(spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>