Ye Li 4e08a510d2 imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers ...

At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

2023-03-29 20:15:42 +02:00

..

upower

imx8ulp: add upower api support

2021-08-09 14:46:51 +02:00

ahab.c

misc: imx: S400_API: Move S400 MU and API to a common place

2022-07-26 11:29:00 +02:00

cgc.c

imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

2023-03-29 20:15:42 +02:00

clock.c

imx8ulp: clock: Fix lcd clock algo

2022-04-21 12:44:23 +02:00

iomux.c

arm: imx8ulp: add iomuxc support

2021-08-09 14:46:51 +02:00

Kconfig

imx: imx8ulp: add ND/LD clock

2022-04-12 17:33:56 +02:00

lowlevel_init.S

arm: imx8ulp: release and configure XRDC at early phase

2021-08-09 14:46:51 +02:00

Makefile

imx8ulp: add upower api support

2021-08-09 14:46:51 +02:00

pcc.c

imx: imx8ulp: add CAAM clock entry

2022-04-12 17:33:56 +02:00

rdc.c

imx: imx8ulp: Reconfigure MRC3 for SRAM0 access

2023-03-29 20:15:42 +02:00

soc.c

imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion

2023-03-29 20:15:42 +02:00