mirror of
https://xff.cz/git/u-boot/
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b60eff31f3
Remove the last uses of symbol offsets in ARM U-Boot. Remove some needless uses of _TEXT_BASE. Remove all _TEXT_BASE definitions. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
451 lines
9.9 KiB
ArmAsm
451 lines
9.9 KiB
ArmAsm
/*
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* armboot - Startup Code for XScale CPU-core
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
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* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
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* Copyright (C) 2003 Kshitij <kshitij@ti.com>
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* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_CPU_PXA25X
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#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
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#error "Init SP address must be set to 0xfffff800 for PXA250"
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#endif
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#endif
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.globl _start
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_start: b reset
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#ifdef CONFIG_SPL_BUILD
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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_hang:
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.word do_hang
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678 /* now 16*4=64 */
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#else
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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_pad: .word 0x12345678 /* now 16*4=64 */
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#endif /* CONFIG_SPL_BUILD */
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.global _end_vect
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_end_vect:
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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#ifdef CONFIG_CPU_PXA25X
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bl lock_cache_for_stack
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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#ifdef CONFIG_CPU_PXA25X
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/*
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* Unlock (actually, disable) the cache now that board_init_f
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* is done. We could do this earlier but we would need to add
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* a new C runtime hook, whereas c_runtime_cpu_setup already
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* exists.
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* As this routine is just a call to cpu_init_crit, let us
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* tail-optimize and do a simple branch here.
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*/
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b cpu_init_crit
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#else
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bx lr
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#endif
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
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#ifndef CONFIG_SPL_BUILD
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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#define I_BIT 0x80
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
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stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
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ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
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ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0 (param register)
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
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str lr, [r13] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction & switch modes.
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.endm
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.macro get_bad_stack_swi
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sub r13, r13, #4 @ space on current stack for scratch reg.
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str r0, [r13] @ save R0's value.
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ldr r0, IRQ_STACK_START_IN @ get data regions start
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str lr, [r0] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r0, #4] @ save spsr in position 1 of saved stack
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ldr lr, [r0] @ restore lr
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ldr r0, [r13] @ restore r0
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add r13, r13, #4 @ pop stack entry
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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#endif /* CONFIG_SPL_BUILD */
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/*
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* exception handlers
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*/
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#ifdef CONFIG_SPL_BUILD
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.align 5
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do_hang:
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bl hang /* hang and never return */
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#else /* !CONFIG_SPL_BUILD */
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack_swi
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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not_used:
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get_bad_stack
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bad_save_user_regs
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bl do_not_used
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#ifdef CONFIG_USE_IRQ
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.align 5
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irq:
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get_irq_stack
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irq_save_user_regs
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bl do_irq
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irq_restore_user_regs
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.align 5
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fiq:
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get_fiq_stack
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/* someone ought to write a more effiction fiq_save_user_regs */
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irq_save_user_regs
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bl do_fiq
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irq_restore_user_regs
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#else
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif
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.align 5
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Enable MMU to use DCache as DRAM.
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*
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* This is useful on PXA25x and PXA26x in early bootstages, where there is no
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* other possible memory available to hold stack.
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*/
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#ifdef CONFIG_CPU_PXA25X
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.macro CPWAIT reg
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mrc p15, 0, \reg, c2, c0, 0
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mov \reg, \reg
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sub pc, pc, #4
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.endm
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lock_cache_for_stack:
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/* Domain access -- enable for all CPs */
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ldr r0, =0x0000ffff
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mcr p15, 0, r0, c3, c0, 0
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/* Point TTBR to MMU table */
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ldr r0, =mmutable
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mcr p15, 0, r0, c2, c0, 0
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/* Kick in MMU, ICache, DCache, BTB */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, #0x1b00
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bic r0, #0x0087
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orr r0, #0x1800
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orr r0, #0x0005
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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/* Unlock Icache, Dcache */
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mcr p15, 0, r0, c9, c1, 1
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mcr p15, 0, r0, c9, c2, 1
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/* Flush Icache, Dcache, BTB */
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mcr p15, 0, r0, c7, c7, 0
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/* Unlock I-TLB, D-TLB */
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mcr p15, 0, r0, c10, c4, 1
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mcr p15, 0, r0, c10, c8, 1
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/* Flush TLB */
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mcr p15, 0, r0, c8, c7, 0
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/* Allocate 4096 bytes of Dcache as RAM */
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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mov r4, #0x00
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mov r5, #0x00
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mov r2, #0x01
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mcr p15, 0, r0, c9, c2, 0
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CPWAIT r0
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/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
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mov r0, #128
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ldr r1, =0xfffff000
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alloc:
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mcr p15, 0, r1, c7, c2, 5
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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strd r4, [r1], #8
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strd r4, [r1], #8
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strd r4, [r1], #8
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strd r4, [r1], #8
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subs r0, #0x01
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bne alloc
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/* Drain pending loads and stores */
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mcr p15, 0, r0, c7, c10, 4
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mov r2, #0x00
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mcr p15, 0, r2, c9, c2, 0
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CPWAIT r0
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mov pc, lr
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.section .mmutable, "a"
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mmutable:
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.align 14
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/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
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.set __base, 0
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.rept 0xfff
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.word (__base << 20) | 0xc12
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.set __base, __base + 1
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.endr
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/* 0xfff00000 : 1:1, cached mapping */
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.word (0xfff << 20) | 0x1c1e
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#endif /* CONFIG_CPU_PXA25X */
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