York Sun f80d6472b4 driver/ddr/fsl: Fix DDR4 driver ...

When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>

2014-09-25 08:36:20 -07:00

..

fsl

driver/ddr/fsl: Fix DDR4 driver

2014-09-25 08:36:20 -07:00