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This converts the following to Kconfig: CONFIG_SPD_EEPROM Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
48 lines
1.4 KiB
Plaintext
48 lines
1.4 KiB
Plaintext
choice
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prompt "Method to determine DDR clock frequency"
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default STATIC_DDR_CLK_FREQ
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depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \
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|| ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \
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|| FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2
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help
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The DDR clock frequency can either be defined statically now at
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build time, or can be determined at run-time via the
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get_board_ddr_clk function.
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config DYNAMIC_DDR_CLK_FREQ
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bool "Run-time DDR clock frequency"
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config STATIC_DDR_CLK_FREQ
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bool "Build-time static DDR clock frequency"
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endchoice
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config DDR_CLK_FREQ
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int "DDR clock frequency in Hz"
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depends on STATIC_DDR_CLK_FREQ
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default 100000000
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help
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The DDR clock frequency, specified in Hz.
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config DDR_SPD
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bool "JEDEC Serial Presence Detect (SPD) support"
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help
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For memory controllers that can utilize it, add enable support for
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using the JEDEC SDP standard.
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config SYS_SPD_BUS_NUM
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int "I2C bus number for DDR SPD"
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depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY
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default 0
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source "drivers/ddr/altera/Kconfig"
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source "drivers/ddr/imx/Kconfig"
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config SPD_EEPROM
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bool "DDR controller makes use of an SPD EEPROM for JEDEC information"
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depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP
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help
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Get DDR timing information from an I2C EEPROM. Common with pluggable
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memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS
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to the I2C address of the SPD EEPROM.
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