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cff451e03f
Add support for different RAM sizes and speed grades on the phyCORE-i.MX8MP. Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz, 4GB 2GHz and 8GB 2GHz RAM. The RAM size and speed grade is detected by the information stored in the EEPROM on the SoM. Co-developed-by: Benjamin Hahn <B.Hahn@phytec.de> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> Co-developed-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Yannic Moog <y.moog@phytec.de> Co-developed-by: Yashwanth Varakala <y.varakala@phytec.de> Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
69 lines
1.2 KiB
C
69 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <env.h>
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#include <init.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
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return 0;
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}
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int board_init(void)
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{
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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switch (get_boot_device()) {
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case SD2_BOOT:
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env_set_ulong("mmcdev", 1);
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break;
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case MMC3_BOOT:
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env_set_ulong("mmcdev", 2);
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break;
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case USB_BOOT:
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printf("Detect USB boot. Will enter fastboot mode!\n");
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env_set_ulong("dofastboot", 1);
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break;
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default:
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break;
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}
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return 0;
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}
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int board_phys_sdram_size(phys_size_t *size)
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{
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if (!size)
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return -EINVAL;
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*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
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return 0;
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}
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