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f172575d92
This adds support for RK806, only the SPI variant has been tested. The communication "protocol" over SPI is the following: - write three bytes: - 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write - 1 byte: LSB register address - 1 byte: MSB register address - write/read length of payload The CRC is always disabled for now. The RK806 technically supports I2C as well, and this should be able to support it without any change, but it wasn't tested. The DT node name prefix for the buck converters has changed in the Device Tree and is now dcdc-reg. The logic for buck converters is however manageable within the current logic inside the rk8xx regulator driver. The same cannot be said for the NLDO and PLDO. Because pmic_bind_children() parses the DT nodes and extracts the LDO index from the DT node name, NLDO and PLDO will have overlapping indices. Therefore, we need a separate logic from the already-existing ldo callbacks. Let's reuse as much as possible though. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
257 lines
4.4 KiB
C
257 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#ifndef _PMIC_RK8XX_H_
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#define _PMIC_RK8XX_H_
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enum {
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REG_SECONDS = 0x00,
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REG_MINUTES,
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REG_HOURS,
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REG_DAYS,
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REG_MONTHS,
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REG_YEARS,
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REG_WEEKS,
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REG_ALARM_SECONDS,
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REG_ALARM_MINUTES,
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REG_ALARM_HOURS,
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REG_ALARM_DAYS,
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REG_ALARM_MONTHS,
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REG_ALARM_YEARS,
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REG_RTC_CTRL = 0x10,
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REG_RTC_STATUS,
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REG_RTC_INT,
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REG_RTC_COMP_LSB,
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REG_RTC_COMP_MSB,
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ID_MSB = 0x17,
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ID_LSB,
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REG_CLK32OUT = 0x20,
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REG_VB_MON,
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REG_THERMAL,
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REG_DCDC_EN,
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REG_LDO_EN,
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REG_SLEEP_SET_OFF1,
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REG_SLEEP_SET_OFF2,
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REG_DCDC_UV_STS,
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REG_DCDC_UV_ACT,
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REG_LDO_UV_STS,
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REG_LDO_UV_ACT,
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REG_DCDC_PG,
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REG_LDO_PG,
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REG_VOUT_MON_TDB,
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REG_BUCK1_CONFIG,
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REG_BUCK1_ON_VSEL,
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REG_BUCK1_SLP_VSEL,
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REG_BUCK1_DVS_VSEL,
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REG_BUCK2_CONFIG,
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REG_BUCK2_ON_VSEL,
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REG_BUCK2_SLP_VSEL,
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REG_BUCK2_DVS_VSEL,
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REG_BUCK3_CONFIG,
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REG_BUCK4_CONFIG,
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REG_BUCK4_ON_VSEL,
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REG_BUCK4_SLP_VSEL,
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REG_BOOST_CONFIG_REG,
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REG_LDO1_ON_VSEL,
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REG_LDO1_SLP_VSEL,
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REG_LDO2_ON_VSEL,
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REG_LDO2_SLP_VSEL,
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REG_LDO3_ON_VSEL,
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REG_LDO3_SLP_VSEL,
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REG_LDO4_ON_VSEL,
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REG_LDO4_SLP_VSEL,
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REG_LDO5_ON_VSEL,
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REG_LDO5_SLP_VSEL,
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REG_LDO6_ON_VSEL,
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REG_LDO6_SLP_VSEL,
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REG_LDO7_ON_VSEL,
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REG_LDO7_SLP_VSEL,
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REG_LDO8_ON_VSEL,
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REG_LDO8_SLP_VSEL,
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REG_DEVCTRL,
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REG_INT_STS1,
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REG_INT_STS_MSK1,
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REG_INT_STS2,
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REG_INT_STS_MSK2,
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REG_IO_POL,
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REG_OTP_VDD_EN,
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REG_H5V_EN,
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REG_SLEEP_SET_OFF,
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REG_BOOST_LDO9_ON_VSEL,
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REG_BOOST_LDO9_SLP_VSEL,
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REG_BOOST_CTRL,
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/* Not sure what this does */
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REG_DCDC_ILMAX = 0x90,
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REG_CHRG_COMP = 0x9a,
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REG_SUP_STS = 0xa0,
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REG_USB_CTRL,
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REG1_CHRG_CTRL,
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REG2_CHRG_CTRL,
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REG3_CHRG_CTRL,
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REG_BAT_CTRL,
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REG_BAT_HTS_TS1,
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REG_BAT_LTS_TS1,
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REG_BAT_HTS_TS2,
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REG_BAT_LTS_TS2,
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REG_TS_CTRL,
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REG_ADC_CTRL,
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REG_ON_SOURCE,
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REG_OFF_SOURCE,
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REG_GGCON,
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REG_GGSTS,
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REG_FRAME_SMP_INTERV,
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REG_AUTO_SLP_CUR_THR,
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REG3_GASCNT_CAL,
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REG2_GASCNT_CAL,
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REG1_GASCNT_CAL,
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REG0_GASCNT_CAL,
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REG3_GASCNT,
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REG2_GASCNT,
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REG1_GASCNT,
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REG0_GASCNT,
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REGH_BAT_CUR_AVG,
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REGL_BAT_CUR_AVG,
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REGH_TS1_ADC,
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REGL_TS1_ADC,
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REGH_TS2_ADC,
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REGL_TS2_ADC,
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REGH_BAT_OCV,
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REGL_BAT_OCV,
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REGH_BAT_VOL,
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REGL_BAT_VOL,
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REGH_RELAX_ENTRY_THRES,
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REGL_RELAX_ENTRY_THRES,
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REGH_RELAX_EXIT_THRES,
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REGL_RELAX_EXIT_THRES,
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REGH_RELAX_VOL1,
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REGL_RELAX_VOL1,
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REGH_RELAX_VOL2,
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REGL_RELAX_VOL2,
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REGH_BAT_CUR_R_CALC,
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REGL_BAT_CUR_R_CALC,
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REGH_BAT_VOL_R_CALC,
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REGL_BAT_VOL_R_CALC,
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REGH_CAL_OFFSET,
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REGL_CAL_OFFSET,
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REG_NON_ACT_TIMER_CNT,
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REGH_VCALIB0,
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REGL_VCALIB0,
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REGH_VCALIB1,
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REGL_VCALIB1,
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REGH_IOFFSET,
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REGL_IOFFSET,
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REG_SOC,
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REG3_REMAIN_CAP,
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REG2_REMAIN_CAP,
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REG1_REMAIN_CAP,
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REG0_REMAIN_CAP,
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REG_UPDAT_LEVE,
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REG3_NEW_FCC,
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REG2_NEW_FCC,
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REG1_NEW_FCC,
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REG0_NEW_FCC,
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REG_NON_ACT_TIMER_CNT_SAVE,
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REG_OCV_VOL_VALID,
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REG_REBOOT_CNT,
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REG_POFFSET,
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REG_MISC_MARK,
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REG_HALT_CNT,
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REGH_CALC_REST,
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REGL_CALC_REST,
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SAVE_DATA19,
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RK808_NUM_OF_REGS,
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};
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enum {
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RK817_REG_SYS_CFG3 = 0xf4,
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};
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enum {
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RK816_REG_DCDC_EN1 = 0x23,
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RK816_REG_DCDC_EN2,
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RK816_REG_DCDC_SLP_EN,
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RK816_REG_LDO_SLP_EN,
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RK816_REG_LDO_EN1 = 0x27,
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RK816_REG_LDO_EN2,
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};
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enum {
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RK806_POWER_SLP_EN0 = 0x06,
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RK806_POWER_SLP_EN1,
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RK806_POWER_SLP_EN2,
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RK806_REG_SYS_CFG3 = 0x72,
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RK806_WDT_REG,
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RK806_ON_SOURCE,
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RK806_OFF_SOURCE
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};
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enum {
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RK805_ID = 0x8050,
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RK806_ID = 0x8060,
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RK808_ID = 0x0000,
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RK809_ID = 0x8090,
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RK816_ID = 0x8160,
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RK817_ID = 0x8170,
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RK818_ID = 0x8180,
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};
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enum {
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RK817_POWER_EN0 = 0xb1,
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RK817_POWER_EN1,
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RK817_POWER_EN2,
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RK817_POWER_EN3,
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};
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#define RK817_POWER_EN_SAVE0 0x99
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#define RK817_POWER_EN_SAVE1 0xa4
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#define RK806_POWER_EN(x) (0x00 + (x))
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/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */
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#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4)))
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#define RK806_POWER_SLP_EN(x) (0x06 + (x))
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#define RK806_ID_MSB 0x5a
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#define RK806_ID_LSB 0x5b
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#define RK817_ID_MSB 0xed
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#define RK817_ID_LSB 0xee
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#define RK8XX_ID_MSK 0xfff0
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#define RK817_PMIC_SYS_CFG3 0xf4
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#define RK817_GPIO_INT_CFG 0xfe
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#define RK8XX_ON_SOURCE 0xae
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#define RK8XX_OFF_SOURCE 0xaf
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#define RK817_BUCK4_CMIN 0xc6
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#define RK817_ON_SOURCE 0xf5
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#define RK817_OFF_SOURCE 0xf6
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#define RK8XX_ON_PWRON BIT(7)
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#define RK8XX_ON_PLUG_IN BIT(6)
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struct reg_data {
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u8 reg;
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u8 val;
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u8 mask;
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};
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struct rk8xx_reg_table {
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char *name;
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u8 reg_ctl;
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u8 reg_vol;
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};
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struct rk8xx_priv {
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int variant;
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};
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int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
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#endif
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