mirror of
https://xff.cz/git/u-boot/
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
131 lines
2.9 KiB
C
131 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 Google, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <asm/arch/wdt.h>
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#include <linux/err.h>
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#define WDT_AST2500 2500
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#define WDT_AST2400 2400
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struct ast_wdt_priv {
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struct ast_wdt *regs;
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};
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static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct ast_wdt_priv *priv = dev_get_priv(dev);
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ulong driver_data = dev_get_driver_data(dev);
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u32 reset_mode = ast_reset_mode_from_flags(flags);
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/* 32 bits at 1MHz is 4294967ms */
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timeout = min_t(u64, timeout, 4294967);
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/* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */
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timeout *= 1000;
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clrsetbits_le32(&priv->regs->ctrl,
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WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
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reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
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if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
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writel(ast_reset_mask_from_flags(flags),
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&priv->regs->reset_mask);
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writel((u32) timeout, &priv->regs->counter_reload_val);
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writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
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/*
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* Setting CLK1MHZ bit is just for compatibility with ast2400 part.
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* On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
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* read-only
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*/
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setbits_le32(&priv->regs->ctrl,
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WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
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return 0;
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}
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static int ast_wdt_stop(struct udevice *dev)
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{
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struct ast_wdt_priv *priv = dev_get_priv(dev);
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clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
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writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask);
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return 0;
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}
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static int ast_wdt_reset(struct udevice *dev)
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{
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struct ast_wdt_priv *priv = dev_get_priv(dev);
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writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
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return 0;
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}
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static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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struct ast_wdt_priv *priv = dev_get_priv(dev);
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int ret;
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ret = ast_wdt_start(dev, 1, flags);
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if (ret)
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return ret;
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while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
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;
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return ast_wdt_stop(dev);
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}
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static int ast_wdt_of_to_plat(struct udevice *dev)
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{
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struct ast_wdt_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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return 0;
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}
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static const struct wdt_ops ast_wdt_ops = {
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.start = ast_wdt_start,
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.reset = ast_wdt_reset,
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.stop = ast_wdt_stop,
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.expire_now = ast_wdt_expire_now,
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};
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static const struct udevice_id ast_wdt_ids[] = {
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{ .compatible = "aspeed,wdt", .data = WDT_AST2500 },
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{ .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
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{ .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
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{}
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};
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static int ast_wdt_probe(struct udevice *dev)
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{
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debug("%s() wdt%u\n", __func__, dev_seq(dev));
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ast_wdt_stop(dev);
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return 0;
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}
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U_BOOT_DRIVER(ast_wdt) = {
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.name = "ast_wdt",
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.id = UCLASS_WDT,
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.of_match = ast_wdt_ids,
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.probe = ast_wdt_probe,
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.priv_auto = sizeof(struct ast_wdt_priv),
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.of_to_plat = ast_wdt_of_to_plat,
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.ops = &ast_wdt_ops,
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};
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