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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <phy.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <linux/mii.h>
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u32 dpmac_to_devdisr[] = {
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[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
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[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
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[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
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[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
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[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
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[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
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[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
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[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
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[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
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[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
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};
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static int is_device_disabled(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
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u32 devdisr2 = in_le32(&gur->devdisr2);
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return dpmac_to_devdisr[dpmac_id] & devdisr2;
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}
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void wriop_dpmac_disable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
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setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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void wriop_dpmac_enable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
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clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
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{
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enum srds_prtcl;
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if (is_device_disabled(dpmac_id + 1))
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return PHY_INTERFACE_MODE_NA;
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switch (lane_prtcl) {
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case SGMII1:
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case SGMII2:
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case SGMII3:
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case SGMII7:
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return PHY_INTERFACE_MODE_SGMII;
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}
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
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return PHY_INTERFACE_MODE_XGMII;
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if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
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return PHY_INTERFACE_MODE_QSGMII;
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return PHY_INTERFACE_MODE_NA;
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}
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void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
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{
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switch (lane_prtcl) {
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case QSGMII_A:
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wriop_init_dpmac(sd, 3, (int)lane_prtcl);
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wriop_init_dpmac(sd, 4, (int)lane_prtcl);
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wriop_init_dpmac(sd, 5, (int)lane_prtcl);
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wriop_init_dpmac(sd, 6, (int)lane_prtcl);
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break;
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case QSGMII_B:
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wriop_init_dpmac(sd, 7, (int)lane_prtcl);
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wriop_init_dpmac(sd, 8, (int)lane_prtcl);
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wriop_init_dpmac(sd, 9, (int)lane_prtcl);
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wriop_init_dpmac(sd, 10, (int)lane_prtcl);
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break;
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}
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}
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#ifdef CONFIG_SYS_FSL_HAS_RGMII
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void fsl_rgmii_init(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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u32 ec;
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#ifdef CONFIG_SYS_FSL_EC1
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
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& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
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if (!ec)
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wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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#ifdef CONFIG_SYS_FSL_EC2
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
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& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
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if (!ec)
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wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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}
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#endif
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