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	When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			80 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			80 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Keystone2: Asynchronous EMIF Configuration
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|  *
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|  * (C) Copyright 2012-2014
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|  *     Texas Instruments Incorporated, <www.ti.com>
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|  */
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| 
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| #include <common.h>
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| #include <asm/arch/hardware.h>
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| #include <asm/ti-common/ti-aemif.h>
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| 
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| #define AEMIF_WAITCYCLE_CONFIG		(KS2_AEMIF_CNTRL_BASE + 0x4)
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| #define AEMIF_NAND_CONTROL		(KS2_AEMIF_CNTRL_BASE + 0x60)
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| #define AEMIF_ONENAND_CONTROL		(KS2_AEMIF_CNTRL_BASE + 0x5c)
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| #define AEMIF_CONFIG(cs)		(KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4))
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| 
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| #define AEMIF_CFG_SELECT_STROBE(v)	((v) ? 1 << 31 : 0)
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| #define AEMIF_CFG_EXTEND_WAIT(v)	((v) ? 1 << 30 : 0)
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| #define AEMIF_CFG_WR_SETUP(v)		(((v) & 0x0f) << 26)
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| #define AEMIF_CFG_WR_STROBE(v)		(((v) & 0x3f) << 20)
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| #define AEMIF_CFG_WR_HOLD(v)		(((v) & 0x07) << 17)
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| #define AEMIF_CFG_RD_SETUP(v)		(((v) & 0x0f) << 13)
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| #define AEMIF_CFG_RD_STROBE(v)		(((v) & 0x3f) << 7)
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| #define AEMIF_CFG_RD_HOLD(v)		(((v) & 0x07) << 4)
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| #define AEMIF_CFG_TURN_AROUND(v)	(((v) & 0x03) << 2)
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| #define AEMIF_CFG_WIDTH(v)		(((v) & 0x03) << 0)
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| 
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| #define set_config_field(reg, field, val)			\
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| 	do {							\
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| 		if (val != -1) {				\
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| 			reg &= ~AEMIF_CFG_##field(0xffffffff);	\
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| 			reg |=	AEMIF_CFG_##field(val);		\
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| 		}						\
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| 	} while (0)
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| 
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| static void aemif_configure(int cs, struct aemif_config *cfg)
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| {
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| 	unsigned long tmp;
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| 
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| 	if (cfg->mode == AEMIF_MODE_NAND) {
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| 		tmp = __raw_readl(AEMIF_NAND_CONTROL);
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| 		tmp |= (1 << cs);
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| 		__raw_writel(tmp, AEMIF_NAND_CONTROL);
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| 
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| 	} else if (cfg->mode == AEMIF_MODE_ONENAND) {
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| 		tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
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| 		tmp |= (1 << cs);
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| 		__raw_writel(tmp, AEMIF_ONENAND_CONTROL);
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| 	}
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| 
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| 	tmp = __raw_readl(AEMIF_CONFIG(cs));
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| 
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| 	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
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| 	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
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| 	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
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| 	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
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| 	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
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| 	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
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| 	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
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| 	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
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| 	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
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| 	set_config_field(tmp, WIDTH,		cfg->width);
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| 
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| 	__raw_writel(tmp, AEMIF_CONFIG(cs));
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| }
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| 
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| void aemif_init(int num_cs, struct aemif_config *config)
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| {
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| 	int cs;
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| 
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| 	if (num_cs > AEMIF_NUM_CS) {
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| 		num_cs = AEMIF_NUM_CS;
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| 		printf("AEMIF: csnum has to be <= 5");
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| 	}
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| 
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| 	for (cs = 0; cs < num_cs; cs++)
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| 		aemif_configure(cs, config + cs);
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| }
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