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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/immap_83xx.h>
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#define NUM_OF_PINS 32
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/** qe_cfg_iopin configure one io pin setting
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*
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* @par_io: pointer to parallel I/O base
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
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int open_drain, int assign)
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{
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u32 dbit_mask;
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u32 dbit_dir;
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u32 dbit_asgn;
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u32 bit_mask;
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u32 tmp_val;
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int offset;
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offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
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/* Calculate pin location and 2bit mask and dir */
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dbit_mask = (u32)(0x3 << offset);
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dbit_dir = (u32)(dir << offset);
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].dir2) :
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in_be32(&par_io->ioport[port].dir1);
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io->ioport[port].podr);
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if (open_drain)
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out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
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else
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out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].ppar2) :
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in_be32(&par_io->ioport[port].ppar1);
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dbit_asgn = (u32)(assign << offset);
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
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}
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}
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#if !defined(CONFIG_PINCTRL)
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/** qe_config_iopin configure one io pin setting
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*
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
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qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
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}
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#endif
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