mirror of
https://xff.cz/git/u-boot/
synced 2025-10-04 17:01:34 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
143 lines
2.8 KiB
C
143 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 - 2016 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <common.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <semihosting.h>
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#include <spl.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ecc_spl_init.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/arch/sys_proto.h>
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#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
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void board_debug_uart_init(void)
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{
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psu_uboot_init();
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}
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#endif
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void board_init_f(ulong dummy)
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{
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#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
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psu_uboot_init();
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#endif
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board_early_init_r();
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#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
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zynqmp_ecc_init();
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#endif
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}
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static void ps_mode_reset(ulong mode)
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{
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(5);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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}
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/*
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* Set default PS_MODE1 which is used for USB ULPI phy reset
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* Also other resets can be connected to this certain pin
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*/
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#ifndef MODE_RESET
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# define MODE_RESET PS_MODE1
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#endif
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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ps_mode_reset(MODE_RESET);
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board_init();
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psu_post_config_data();
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}
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#endif
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static u32 jtag_boot_device(void)
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{
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return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
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spl_boot_list[1] = BOOT_DEVICE_MMC2;
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if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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spl_boot_list[2] = jtag_boot_device();
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}
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u32 spl_boot_device(void)
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{
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u32 reg = 0;
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u8 bootmode;
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#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
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/* Change default boot mode at run-time */
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reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE;
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writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
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&crlapb_base->boot_mode);
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#else
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reg = readl(&crlapb_base->boot_mode);
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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#endif
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bootmode = reg & BOOT_MODES_MASK;
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switch (bootmode) {
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case JTAG_MODE:
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return jtag_boot_device();
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#ifdef CONFIG_SPL_MMC
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case SD_MODE1:
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case SD1_LSHFT_MODE: /* not working on silicon v1 */
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return BOOT_DEVICE_MMC2;
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case SD_MODE:
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case EMMC_MODE:
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return BOOT_DEVICE_MMC1;
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#endif
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#ifdef CONFIG_SPL_DFU
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case USB_MODE:
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return BOOT_DEVICE_DFU;
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#endif
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#ifdef CONFIG_SPL_SATA
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case SW_SATA_MODE:
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return BOOT_DEVICE_SATA;
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#endif
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#ifdef CONFIG_SPL_SPI
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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return BOOT_DEVICE_SPI;
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#endif
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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return 0;
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}
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#endif
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