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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RZ/G2L family memory map tables
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/u-boot.h>
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#include <cpu_func.h>
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#define RZG2L_NR_REGIONS 16
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/*
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* RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of
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* which the first 128 MiB is reserved by TF-A.
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*/
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static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x03F00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x47E00000UL,
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.phys = 0x47E00000UL,
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.size = 0xF8200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rzg2l_mem_map;
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DECLARE_GLOBAL_DATA_PTR;
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#define debug_memmap(i, map) \
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debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \
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i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
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void enable_caches(void)
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{
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unsigned int bank, i = 0;
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u64 start, size;
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/* Create map for register access */
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rzg2l_mem_map[i].virt = 0x0ULL;
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rzg2l_mem_map[i].phys = 0x0ULL;
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rzg2l_mem_map[i].size = 0x40000000ULL;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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/* Generate entries for DRAM in 32bit address space */
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = gd->bd->bi_dram[bank].start;
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size = gd->bd->bi_dram[bank].size;
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/* Skip empty DRAM banks */
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if (!size)
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continue;
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/* Mark memory reserved by ATF as cacheable too. */
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if (start == 0x48000000) {
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/* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
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rzg2l_mem_map[i].virt = 0x40000000ULL;
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rzg2l_mem_map[i].phys = 0x40000000ULL;
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rzg2l_mem_map[i].size = 0x03F00000ULL;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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start = 0x47E00000ULL;
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size += 0x00200000ULL;
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}
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rzg2l_mem_map[i].virt = start;
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rzg2l_mem_map[i].phys = start;
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rzg2l_mem_map[i].size = size;
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rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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debug_memmap(i, rzg2l_mem_map);
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i++;
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}
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/* Zero out the remaining regions. */
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for (; i < RZG2L_NR_REGIONS; i++) {
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rzg2l_mem_map[i].virt = 0;
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rzg2l_mem_map[i].phys = 0;
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rzg2l_mem_map[i].size = 0;
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rzg2l_mem_map[i].attrs = 0;
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debug_memmap(i, rzg2l_mem_map);
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}
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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