mirror of
https://xff.cz/git/u-boot/
synced 2025-10-08 19:55:12 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
140 lines
2.7 KiB
C
140 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <env.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <semihosting.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <fsl_ifc.h>
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#include <i2c.h>
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#include <fsl_csu.h>
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#include <asm/arch/fdt.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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if (semihosting_enabled())
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return BOOT_DEVICE_SMH;
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#ifdef CONFIG_SPL_MMC
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return BOOT_DEVICE_MMC1;
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#endif
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#ifdef CONFIG_SPL_NAND_SUPPORT
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return BOOT_DEVICE_NAND;
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#endif
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#ifdef CONFIG_QSPI_BOOT
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return BOOT_DEVICE_NOR;
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
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/*
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* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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* SMMU must be reset in bypass mode.
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* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_SCR0, val);
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val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_NSCR0, val);
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#endif
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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}
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void tzpc_init(void)
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{
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/*
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* Mark the whole OCRAM as non-secure, otherwise DMA devices cannot
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* access it. This is for example necessary for MMC boot.
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*/
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#ifdef TZPCR0SIZE_BASE
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out_le32(TZPCR0SIZE_BASE, 0);
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#endif
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}
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__weak int init_func_vid(void)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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icache_enable();
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tzpc_init();
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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if (IS_ENABLED(CONFIG_DEBUG_UART))
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debug_uart_init();
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board_early_init_f();
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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timer_init();
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#ifdef CONFIG_ARCH_LS2080A
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env_init();
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#endif
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get_clocks();
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preloader_console_init();
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spl_set_bd();
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#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
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#ifdef CONFIG_SPL_I2C
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i2c_init_all();
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#endif
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#endif
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#if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
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defined(CONFIG_ARCH_LX2160A) || \
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defined(CONFIG_ARCH_LX2162A))
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init_func_vid();
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#endif
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dram_init();
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#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
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qspi_ahb_init();
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#endif
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}
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#ifdef CONFIG_SPL_OS_BOOT
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/*
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* Return
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* 0 if booting into OS is selected
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* 1 if booting into U-Boot is selected
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*/
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int spl_start_uboot(void)
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{
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env_init();
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if (env_get_yesno("boot_os") != 0)
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return 0;
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return 1;
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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#endif /* CONFIG_SPL_BUILD */
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