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54ba653ab6
Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
225 lines
6.3 KiB
C
225 lines
6.3 KiB
C
/*
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* SPI flash internal definitions
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*
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* Copyright (C) 2008 Atmel Corporation
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* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SF_INTERNAL_H_
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#define _SF_INTERNAL_H_
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#include <linux/types.h>
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#include <linux/compiler.h>
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/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
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enum spi_dual_flash {
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SF_SINGLE_FLASH = 0,
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SF_DUAL_STACKED_FLASH = 1 << 0,
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SF_DUAL_PARALLEL_FLASH = 1 << 1,
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};
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/* Enum list - Full read commands */
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enum spi_read_cmds {
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ARRAY_SLOW = 1 << 0,
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ARRAY_FAST = 1 << 1,
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DUAL_OUTPUT_FAST = 1 << 2,
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DUAL_IO_FAST = 1 << 3,
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QUAD_OUTPUT_FAST = 1 << 4,
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QUAD_IO_FAST = 1 << 5,
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};
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/* Normal - Extended - Full command set */
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#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
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#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
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#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
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/* sf param flags */
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enum {
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SECT_4K = 1 << 0,
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SECT_32K = 1 << 1,
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E_FSR = 1 << 2,
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SST_BP = 1 << 3,
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SST_WP = 1 << 4,
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WR_QPP = 1 << 5,
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};
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#define SST_WR (SST_BP | SST_WP)
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#define SPI_FLASH_3B_ADDR_LEN 3
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#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
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#define SPI_FLASH_16MB_BOUN 0x1000000
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/* CFI Manufacture ID's */
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#define SPI_FLASH_CFI_MFR_SPANSION 0x01
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#define SPI_FLASH_CFI_MFR_STMICRO 0x20
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#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
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#define SPI_FLASH_CFI_MFR_WINBOND 0xef
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/* Erase commands */
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#define CMD_ERASE_4K 0x20
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#define CMD_ERASE_32K 0x52
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#define CMD_ERASE_CHIP 0xc7
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#define CMD_ERASE_64K 0xd8
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/* Write commands */
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#define CMD_WRITE_STATUS 0x01
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#define CMD_PAGE_PROGRAM 0x02
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#define CMD_WRITE_DISABLE 0x04
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#define CMD_READ_STATUS 0x05
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#define CMD_QUAD_PAGE_PROGRAM 0x32
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#define CMD_READ_STATUS1 0x35
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_READ_CONFIG 0x35
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#define CMD_FLAG_STATUS 0x70
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/* Read commands */
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#define CMD_READ_ARRAY_SLOW 0x03
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#define CMD_READ_ARRAY_FAST 0x0b
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#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
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#define CMD_READ_DUAL_IO_FAST 0xbb
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#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
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#define CMD_READ_QUAD_IO_FAST 0xeb
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#define CMD_READ_ID 0x9f
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/* Bank addr access commands */
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#ifdef CONFIG_SPI_FLASH_BAR
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# define CMD_BANKADDR_BRWR 0x17
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# define CMD_BANKADDR_BRRD 0x16
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# define CMD_EXTNADDR_WREAR 0xC5
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# define CMD_EXTNADDR_RDEAR 0xC8
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#endif
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/* Common status */
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#define STATUS_WIP (1 << 0)
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#define STATUS_QEB_WINSPAN (1 << 1)
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#define STATUS_QEB_MXIC (1 << 6)
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#define STATUS_PEC (1 << 7)
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#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
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#define STATUS_SRWD (1 << 7) /* SR write protect */
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#endif
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/* Flash timeout values */
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#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
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#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
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#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
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/* SST specific */
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#ifdef CONFIG_SPI_FLASH_SST
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# define CMD_SST_BP 0x02 /* Byte Program */
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# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
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int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
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const void *buf);
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int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
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const void *buf);
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#endif
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/**
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* struct spi_flash_params - SPI/QSPI flash device params structure
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*
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* @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
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* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
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* @ext_jedec: Device ext_jedec ID
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* @sector_size: Sector size of this device
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* @nr_sectors: No.of sectors on this device
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* @e_rd_cmd: Enum list for read commands
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* @flags: Important param, for flash specific behaviour
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*/
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struct spi_flash_params {
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const char *name;
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u32 jedec;
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u16 ext_jedec;
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u32 sector_size;
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u32 nr_sectors;
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u8 e_rd_cmd;
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u16 flags;
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};
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extern const struct spi_flash_params spi_flash_params_table[];
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/* Send a single-byte command to the device and read the response */
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int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
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/*
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* Send a multi-byte command to the device and read the response. Used
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* for flash array reads, etc.
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*/
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int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
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size_t cmd_len, void *data, size_t data_len);
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/*
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* Send a multi-byte command to the device followed by (optional)
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* data. Used for programming the flash array, etc.
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*/
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int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
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const void *data, size_t data_len);
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/* Flash erase(sectors) operation, support all possible erase commands */
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int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
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/* Read the status register */
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int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
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/* Program the status register */
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int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
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/* Read the config register */
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int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
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/* Program the config register */
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int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
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/* Enable writing on the SPI flash */
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static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
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{
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return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
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}
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/* Disable writing on the SPI flash */
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static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
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{
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return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
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}
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/*
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* Send the read status command to the device and wait for the wip
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* (write-in-progress) bit to clear itself.
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*/
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int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
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/*
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* Used for spi_flash write operation
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* - SPI claim
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* - spi_flash_cmd_write_enable
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* - spi_flash_cmd_write
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* - spi_flash_cmd_wait_ready
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* - SPI release
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*/
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int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
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size_t cmd_len, const void *buf, size_t buf_len);
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/*
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* Flash write operation, support all possible write commands.
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* Write the requested data out breaking it up into multiple write
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* commands as needed per the write size.
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*/
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int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
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size_t len, const void *buf);
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/*
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* Same as spi_flash_cmd_read() except it also claims/releases the SPI
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* bus. Used as common part of the ->read() operation.
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*/
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int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
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size_t cmd_len, void *data, size_t data_len);
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/* Flash read operation, support all possible read commands */
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int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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size_t len, void *data);
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#endif /* _SF_INTERNAL_H_ */
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