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27ce9e4290
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.
*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."
*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."
Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.
commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults.
Signed-off-by: Pekon Gupta <pekon@ti.com>
271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/mtd/nand_ecc.h>
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static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
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static nand_info_t mtd;
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static struct nand_chip nand_chip;
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#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
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#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
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/*
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* NAND command for small page NAND devices (512)
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*/
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static int nand_command(int block, int page, uint32_t offs,
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u8 cmd)
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{
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struct nand_chip *this = mtd.priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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while (!this->dev_ready(&mtd))
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;
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/* Begin command latch cycle */
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this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
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this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
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this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
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NAND_CTRL_ALE); /* A[24:17] */
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#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
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/* One more address cycle for devices > 32MiB */
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this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[28:25] */
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#endif
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/* Latch in address */
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this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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while (!this->dev_ready(&mtd))
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;
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return 0;
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}
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#else
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/*
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* NAND command for large page NAND devices (2k)
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*/
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static int nand_command(int block, int page, uint32_t offs,
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u8 cmd)
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{
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struct nand_chip *this = mtd.priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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void (*hwctrl)(struct mtd_info *mtd, int cmd,
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unsigned int ctrl) = this->cmd_ctrl;
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while (!this->dev_ready(&mtd))
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;
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/* Emulate NAND_CMD_READOOB */
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if (cmd == NAND_CMD_READOOB) {
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offs += CONFIG_SYS_NAND_PAGE_SIZE;
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cmd = NAND_CMD_READ0;
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}
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/* Shift the offset from byte addressing to word addressing. */
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if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
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offs >>= 1;
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/* Begin command latch cycle */
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hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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hwctrl(&mtd, offs & 0xff,
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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/* Row address */
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hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
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hwctrl(&mtd, ((page_addr >> 8) & 0xff),
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NAND_CTRL_ALE); /* A[27:20] */
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* One more address cycle for devices > 128MiB */
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hwctrl(&mtd, (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[31:28] */
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#endif
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/* Latch in address */
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hwctrl(&mtd, NAND_CMD_READSTART,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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while (!this->dev_ready(&mtd))
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;
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return 0;
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}
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#endif
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static int nand_is_bad_block(int block)
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{
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struct nand_chip *this = mtd.priv;
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nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
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NAND_CMD_READOOB);
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/*
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* Read one byte (or two if it's a 16 bit chip).
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*/
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if (this->options & NAND_BUSWIDTH_16) {
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if (readw(this->IO_ADDR_R) != 0xffff)
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return 1;
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} else {
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if (readb(this->IO_ADDR_R) != 0xff)
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return 1;
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}
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return 0;
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}
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#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
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static int nand_read_page(int block, int page, uchar *dst)
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{
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struct nand_chip *this = mtd.priv;
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u_char ecc_calc[ECCTOTAL];
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u_char ecc_code[ECCTOTAL];
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u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
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int i;
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int eccsize = CONFIG_SYS_NAND_ECCSIZE;
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int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
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int eccsteps = ECCSTEPS;
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uint8_t *p = dst;
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nand_command(block, page, 0, NAND_CMD_READOOB);
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this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
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nand_command(block, page, 0, NAND_CMD_READ0);
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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this->ecc.hwctl(&mtd, NAND_ECC_READ);
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this->read_buf(&mtd, p, eccsize);
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this->ecc.calculate(&mtd, p, &ecc_calc[i]);
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this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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#else
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static int nand_read_page(int block, int page, void *dst)
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{
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struct nand_chip *this = mtd.priv;
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u_char ecc_calc[ECCTOTAL];
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u_char ecc_code[ECCTOTAL];
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u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
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int i;
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int eccsize = CONFIG_SYS_NAND_ECCSIZE;
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int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
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int eccsteps = ECCSTEPS;
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uint8_t *p = dst;
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nand_command(block, page, 0, NAND_CMD_READ0);
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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if (this->ecc.mode != NAND_ECC_SOFT)
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this->ecc.hwctl(&mtd, NAND_ECC_READ);
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this->read_buf(&mtd, p, eccsize);
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this->ecc.calculate(&mtd, p, &ecc_calc[i]);
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}
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this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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eccsteps = ECCSTEPS;
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p = dst;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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/* No chance to do something with the possible error message
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* from correct_data(). We just hope that all possible errors
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* are corrected by this routine.
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*/
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this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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#endif
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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{
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unsigned int block, lastblock;
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unsigned int page;
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/*
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* offs has to be aligned to a page address!
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*/
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block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
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lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
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page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
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while (block <= lastblock) {
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if (!nand_is_bad_block(block)) {
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/*
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* Skip bad blocks
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*/
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while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
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nand_read_page(block, page, dst);
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dst += CONFIG_SYS_NAND_PAGE_SIZE;
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page++;
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}
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page = 0;
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} else {
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lastblock++;
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}
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block++;
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}
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return 0;
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}
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/* nand_init() - initialize data to make nand usable by SPL */
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void nand_init(void)
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{
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/*
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* Init board specific nand support
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*/
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mtd.priv = &nand_chip;
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nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
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(void __iomem *)CONFIG_SYS_NAND_BASE;
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board_nand_init(&nand_chip);
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#ifdef CONFIG_SPL_NAND_SOFTECC
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if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
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nand_chip.ecc.calculate = nand_calculate_ecc;
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nand_chip.ecc.correct = nand_correct_data;
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}
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#endif
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, 0);
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}
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/* Unselect after operation */
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void nand_deselect(void)
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{
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, -1);
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}
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