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34e026f9b1
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
38 lines
1.3 KiB
Makefile
38 lines
1.3 KiB
Makefile
#
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# Copyright 2008-2014 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# Version 2 as published by the Free Software Foundation.
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#
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obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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ifdef CONFIG_DDR_SPD
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SPD := y
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endif
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ifdef CONFIG_SPD_EEPROM
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SPD := y
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endif
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ifdef SPD
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obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
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endif
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obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
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obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
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obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
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