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https://xff.cz/git/u-boot/
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72fd3838c6
The arch_preboot_os function used in boards using R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) is common. This makes rcar-gen2-common/common.c file providing common function for R-Car ARM SoC, and moves this function to this file. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
147 lines
3.2 KiB
C
147 lines
3.2 KiB
C
/*
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* board/renesas/gose/gose.c
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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u32 stc;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* CPU frequency setting. Set to 1.5GHz */
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stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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/* QoS */
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qos_init();
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}
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#define TMU0_MSTP125 (1 << 25)
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#define SCIF0_MSTP721 (1 << 21)
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#define ETHER_MSTP813 (1 << 13)
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int board_early_init_f(void)
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{
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/* TMU0 */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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return 0;
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}
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#define PUPR5 0xE6060114
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#define PUPR5_ETH 0x3FFC0000
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#define PUPR5_ETH_MAGIC (1 << 27)
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7793_pinmux_init();
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/* ETHER Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
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gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
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gpio_direction_output(GPIO_GP_5_22, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_5_22, 1);
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udelay(1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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int ret = -ENODEV;
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u32 val;
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unsigned char enetaddr[6];
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#ifdef CONFIG_SH_ETHER
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ret = sh_eth_initialize(bis);
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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#endif
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return ret;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RMOBILE_BOARD_STRING
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};
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void reset_cpu(ulong addr)
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{
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u8 val;
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i2c_set_bus_num(2); /* PowerIC connected to ch2 */
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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