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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
191 lines
5.5 KiB
C
191 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011 Freescale Semiconductor
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* Copyright 2020 NXP
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* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* This file provides support for the QIXIS of some Freescale reference boards.
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*/
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#ifndef __QIXIS_H_
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#define __QIXIS_H_
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struct qixis {
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u8 id; /* ID value uniquely identifying each QDS board type */
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u8 arch; /* Board version information */
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u8 scver; /* QIXIS Version Register */
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u8 model; /* Information of software programming model version */
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u8 tagdata;
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u8 ctl_sys;
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u8 aux; /* Auxiliary Register,0x06 */
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u8 clk_spd;
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u8 stat_dut;
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u8 stat_sys;
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u8 stat_alrm;
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u8 present;
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u8 present2; /* Presence Status Register 2,0x0c */
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u8 rcw_ctl;
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u8 ctl_led;
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u8 i2cblk;
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u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
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u8 rcfg_st;
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u8 dcm_ad;
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u8 dcm_da;
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u8 dcmd;
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u8 dmsg;
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u8 gdc;
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u8 gdd; /* DCM Debug Data Register,0x17 */
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u8 dmack;
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u8 res1;
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u8 sdhc1;
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u8 sdhc2;
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u8 stat_pres3;
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u8 los_stat;
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u8 usb_ctl;
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u8 watch; /* Watchdog Register,0x1F */
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u8 pwr_ctl[2]; /* Power Control Register,0x20 */
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u8 res2[2];
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u8 pwr_stat[4]; /* Power Status Register,0x24 */
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u8 res3[8];
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u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
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u8 res4[2];
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u8 sclk[3]; /* Clock Configuration Registers,0x34 */
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u8 res5;
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u8 dclk[3];
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u8 res6;
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u8 clk_dspd[3];
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u8 res7;
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u8 rst_ctl; /* Reset Control Register,0x40 */
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u8 rst_stat; /* Reset Status Register */
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u8 rst_rsn; /* Reset Reason Register */
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u8 rst_frc[2]; /* Reset Force Registers,0x43 */
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u8 res8[11];
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u8 brdcfg[16]; /* Board Configuration Register,0x50 */
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u8 dutcfg[16];
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u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
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u8 rcw_data;
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u8 res9[5];
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u8 post_ctl;
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u8 post_stat;
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u8 post_dat[2];
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u8 pi_d[4];
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u8 gpio_io[4];
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u8 gpio_dir[4];
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u8 res10[20];
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u8 rjtag_ctl;
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u8 rjtag_dat;
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u8 res11[2];
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u8 trig_src[4];
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u8 trig_dst[4];
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u8 trig_stat;
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u8 res12[3];
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u8 trig_ctr[4];
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u8 res13[16];
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u8 clk_freq[6]; /* Clock Measurement Registers */
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u8 res_c6[8];
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u8 clk_base[2]; /* Clock Frequency Base Reg */
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u8 res_d0[8];
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u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
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u8 res_c0[6];
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u8 aux2[4]; /* Auxiliary Registers,0xE0 */
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u8 res14[10];
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u8 aux_ad;
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u8 aux_da;
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u8 res15[16];
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};
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u8 qixis_read(unsigned int reg);
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void qixis_write(unsigned int reg, u8 value);
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u16 qixis_read_minor(void);
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char *qixis_read_time(char *result);
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char *qixis_read_tag(char *buf);
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const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
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#ifdef CFG_SYS_I2C_FPGA_ADDR
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u8 qixis_read_i2c(unsigned int reg);
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void qixis_write_i2c(unsigned int reg, u8 value);
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#endif
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#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR)
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#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
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#define QIXIS_WRITE(reg, value) \
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qixis_write_i2c(offsetof(struct qixis, reg), value)
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#else
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#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
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#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
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#endif
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#ifdef CFG_SYS_I2C_FPGA_ADDR
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#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
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#define QIXIS_WRITE_I2C(reg, value) \
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qixis_write_i2c(offsetof(struct qixis, reg), value)
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#endif
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/* Use for SDHC adapter card type identification and operation */
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
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#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
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#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
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#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */
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#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */
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#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
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#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
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#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */
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#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */
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#define QIXIS_SDCLKIN 0x08
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#define QIXIS_SDCLKOUT 0x02
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#define QIXIS_DAT5_6_7 0X02
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#define QIXIS_DAT4 0X01
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#define QIXIS_EVDD_BY_SDHC_VS 0x0c
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#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
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defined(CONFIG_TARGET_LX2160ARDB)
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#define QIXIS_XMAP_MASK 0x07
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#define QIXIS_RST_CTL_RESET_EN 0x30
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x20
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_QSPI 0xff
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SD
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#define QIXIS_LBMAP_EMMC
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#define QIXIS_RCW_SRC_SD 0x08
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#define QIXIS_RCW_SRC_EMMC 0x09
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#define NON_EXTENDED_DUTCFG
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#endif
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#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#endif
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/*
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* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
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*/
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static inline u8 qixis_esdhc_detect_quirk(void)
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{
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/*
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* SDHC1 Card ID:
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* Specifies the type of card installed in the SDHC1 adapter slot.
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* 000= (reserved)
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* 001= eMMC V4.5 adapter is installed.
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* 010= SD/MMC 3.3V adapter is installed.
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* 011= eMMC V4.4 adapter is installed.
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* 100= eMMC V5.0 adapter is installed.
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* 101= MMC card/Legacy (3.3V) adapter is installed.
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* 110= SDCard V2/V3 adapter installed.
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* 111= no adapter is installed.
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*/
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return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
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QIXIS_ESDHC_NO_ADAPTER);
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}
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#endif
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