Ley Foon Tan 35b9800ff2 arm: socfpga: Add misc support for Arria 10 ...

Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

2017-05-18 11:33:18 +02:00

..

base_addr_a10.h

arm: socfpga: Add A10 macros

2017-05-18 11:33:17 +02:00

base_addr_ac5.h

ARM: socfpga: rename the cyclone5 and arria5 base address file

2015-11-30 13:30:19 +01:00

boot0.h

ARM: socfpga: boot0 hook: remove macro from boot0 header file

2017-04-14 14:06:42 +02:00

clock_manager_arria10.h

arm: socfpga: Add clock driver for Arria 10

2017-05-18 11:33:17 +02:00

clock_manager_gen5.h

arm: socfpga: Restructure clock manager driver

2017-05-18 11:33:16 +02:00

clock_manager.h

arm: socfpga: Add clock driver for Arria 10

2017-05-18 11:33:17 +02:00

fpga_manager.h

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freeze_controller.h

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gpio.h

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misc.h

arm: socfpga: Add misc support for Arria 10

2017-05-18 11:33:18 +02:00

nic301.h

…

pinmux.h

arm: socfpga: Add pinmux for Arria 10

2017-05-18 11:33:18 +02:00

reset_manager_arria10.h

arm: socfpga: Add reset driver support for Arria 10

2017-05-18 11:33:17 +02:00

reset_manager_gen5.h

arm: socfpga: Restructure reset manager driver

2017-05-18 11:33:17 +02:00

reset_manager.h

arm: socfpga: Add reset driver support for Arria 10

2017-05-18 11:33:17 +02:00

scan_manager.h

…

scu.h

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sdram_arria10.h

arm: socfpga: Add sdram header file for Arria 10

2017-05-18 11:33:18 +02:00

sdram.h

ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-10-27 08:03:07 +02:00

system_manager_arria10.h

arm: socfpga: Add system manager for Arria 10

2017-05-18 11:33:18 +02:00

system_manager_gen5.h

arm: socfpga: Restructure system manager

2017-05-18 11:33:17 +02:00

system_manager.h

arm: socfpga: Add system manager for Arria 10

2017-05-18 11:33:18 +02:00

timer.h

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