Patrick Delaunay bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator ...

To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

2019-02-09 07:50:57 -05:00

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microchip,pic32-clock.txt

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nvidia,tegra20-car.txt

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rockchip,rk3188-cru.txt

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rockchip,rk3288-cru.txt

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rockchip,rk3288-dmc.txt

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rockchip,rk3368-dmc.txt

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

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rockchip,rk3399-dmc.txt

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rockchip.txt

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snps,hsdk-cgu.txt

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st,stm32-rcc.txt

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st,stm32h7-rcc.txt

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2017-09-22 07:40:01 -04:00

st,stm32mp1.txt

clk: stm32mp1: correctly handle Clock Spreading Generator

2019-02-09 07:50:57 -05:00

ti,sci-clk.txt

clk: Introduce TI System Control Interface (TI SCI) clock driver

2018-09-11 08:32:55 -04:00