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ef639e6f70
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
37 lines
682 B
C
37 lines
682 B
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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timer_init();
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/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
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if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
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gd->arch.running_on_hw = 0;
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else
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gd->arch.running_on_hw = 1;
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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cache_init();
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return 0;
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}
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int arch_early_init_r(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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