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17b7efe25b
Add support for the Amlogic G12A SoC, which is a mix between the new physical memory mapping of AXG and the functionnalities of the previous Amlogic GXL/GXM SoCs. To handle the internal ethernet PHY, the Amlogic G12A SoCs now embeds a dedicated PLL to feed the internal PHY. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __G12A_H__
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#define __G12A_H__
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#define G12A_AOBUS_BASE 0xff800000
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#define G12A_PERIPHS_BASE 0xff634400
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#define G12A_HIU_BASE 0xff63c000
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#define G12A_ETH_PHY_BASE 0xff64c000
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#define G12A_ETH_BASE 0xff3f0000
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/* Always-On Peripherals registers */
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#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
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#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
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#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
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#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
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#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
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#define G12A_AO_BOOT_DEVICE 0xF
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#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_MEM_SIZE_SHIFT 16
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#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
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#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
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#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
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#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
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#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
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#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define G12A_ETH_REG_0_CLK_EN BIT(12)
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#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
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#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
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#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
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#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
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#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
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#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
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#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
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#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
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#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
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#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
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#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
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#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
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/* HIU registers */
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#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
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#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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#endif /* __G12A_H__ */
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