mirror of
				https://xff.cz/git/u-boot/
				synced 2025-10-31 02:15:45 +01:00 
			
		
		
		
	Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial@402D0000 Out: serial@402D0000 Err: serial@402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
		
			
				
	
	
		
			427 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			427 lines
		
	
	
		
			9.0 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /*
 | |
|  * Copyright 2016 Freescale Semiconductor, Inc.
 | |
|  *
 | |
|  * This program is free software; you can redistribute it and/or modify
 | |
|  * it under the terms of the GNU General Public License version 2 as
 | |
|  * published by the Free Software Foundation.
 | |
|  */
 | |
| 
 | |
| /dts-v1/;
 | |
| 
 | |
| #include "imx7ulp.dtsi"
 | |
| 
 | |
| / {
 | |
| 	model = "NXP i.MX7ULP EVK";
 | |
| 	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
 | |
| 
 | |
| 	chosen {
 | |
| 		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
 | |
| 		stdout-path = &lpuart4;
 | |
| 	};
 | |
| 
 | |
| 	bcmdhd_wlan_0: bcmdhd_wlan@0 {
 | |
| 		compatible = "android,bcmdhd_wlan";
 | |
| 		wlreg_on-supply = <&wlreg_on>;
 | |
| 		bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
 | |
| 		bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
 | |
| 	};
 | |
| 
 | |
| 	memory {
 | |
| 		device_type = "memory";
 | |
| 		reg = <0x60000000 0x40000000>;
 | |
| 	};
 | |
| 
 | |
| 	backlight {
 | |
| 		compatible = "gpio-backlight";
 | |
| 		pinctrl-names = "default";
 | |
| 		pinctrl-0 = <&pinctrl_backlight>;
 | |
| 		gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
 | |
| 		default-on;
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	mipi_dsi_reset: mipi-dsi-reset {
 | |
| 		compatible = "gpio-reset";
 | |
| 		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 | |
| 		reset-delay-us = <1000>;
 | |
| 		#reset-cells = <0>;
 | |
| 	};
 | |
| 
 | |
| 	regulators {
 | |
| 		compatible = "simple-bus";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 
 | |
| 		wlreg_on: fixedregulator@100 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			regulator-name = "wlreg_on";
 | |
| 			gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 | |
| 			startup-delay-us = <100>;
 | |
| 			enable-active-high;
 | |
| 		};
 | |
| 
 | |
| 		reg_usb_otg1_vbus: regulator@0 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <0>;
 | |
| 			pinctrl-names = "default";
 | |
| 			pinctrl-0 = <&pinctrl_usb_otg1>;
 | |
| 			regulator-name = "usb_otg1_vbus";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
 | |
| 			enable-active-high;
 | |
| 		};
 | |
| 
 | |
| 		reg_vsd_3v3: regulator@1 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <1>;
 | |
| 			regulator-name = "VSD_3V3";
 | |
| 			regulator-min-microvolt = <3300000>;
 | |
| 			regulator-max-microvolt = <3300000>;
 | |
| 			gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 | |
| 			enable-active-high;
 | |
| 		};
 | |
| 
 | |
| 		reg_vsd_3v3b: regulator@2 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <2>;
 | |
| 			regulator-name = "VSD_3V3B";
 | |
| 			regulator-min-microvolt = <3300000>;
 | |
| 			regulator-max-microvolt = <3300000>;
 | |
| 			gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
 | |
| 			enable-active-high;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	extcon_usb1: extcon_usb1 {
 | |
| 		compatible = "linux,extcon-usb-gpio";
 | |
| 		id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 | |
| 		pinctrl-names = "default";
 | |
| 		pinctrl-0 = <&pinctrl_extcon_usb1>;
 | |
| 	};
 | |
| 
 | |
| 	pf1550-rpmsg {
 | |
| 		compatible = "fsl,pf1550-rpmsg";
 | |
| 		sw1_reg: SW1 {
 | |
| 				regulator-name = "SW1";
 | |
| 				regulator-min-microvolt = <600000>;
 | |
| 				regulator-max-microvolt = <1387500>;
 | |
| 				regulator-boot-on;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		sw2_reg: SW2 {
 | |
| 				regulator-name = "SW2";
 | |
| 				regulator-min-microvolt = <600000>;
 | |
| 				regulator-max-microvolt = <1387500>;
 | |
| 				regulator-boot-on;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		sw3_reg: SW3 {
 | |
| 				regulator-name = "SW3";
 | |
| 				regulator-min-microvolt = <1800000>;
 | |
| 				regulator-max-microvolt = <3300000>;
 | |
| 				regulator-boot-on;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		vref_reg: VREFDDR {
 | |
| 				regulator-name = "VREFDDR";
 | |
| 				regulator-min-microvolt = <1200000>;
 | |
| 				regulator-max-microvolt = <1200000>;
 | |
| 				regulator-boot-on;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		vldo1_reg: LDO1 {
 | |
| 				regulator-name = "LDO1";
 | |
| 				regulator-min-microvolt = <750000>;
 | |
| 				regulator-max-microvolt = <3300000>;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		vldo2_reg: LDO2 {
 | |
| 				regulator-name = "LDO2";
 | |
| 				regulator-min-microvolt = <1800000>;
 | |
| 				regulator-max-microvolt = <3300000>;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		vldo3_reg: LDO3 {
 | |
| 				regulator-name = "LDO3";
 | |
| 				regulator-min-microvolt = <750000>;
 | |
| 				regulator-max-microvolt = <3300000>;
 | |
| 				regulator-always-on;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &iomuxc1 {
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_hog_1>;
 | |
| 
 | |
| 	imx7ulp-evk {
 | |
| 		pinctrl_hog_1: hoggrp-1 {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC10__PTC10		0x30100		/* USDHC0 CD */
 | |
| 				ULP1_PAD_PTC1__PTC1		0x20100
 | |
| 				ULP1_PAD_PTD0__PTD0		0x30100		/* USDHC0 RST */
 | |
| 				ULP1_PAD_PTE13__PTE13		0x30103		/* USDHC1 CD */
 | |
| 				ULP1_PAD_PTE12__PTE12		0x30103		/* USDHC1 WP */
 | |
| 				ULP1_PAD_PTE14__SDHC1_VS	0x843		/* USDHC1 VSEL */
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_backlight: backlight_grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTF2__PTF2		0x20100
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpi2c5: lpi2c5grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC4__LPI2C5_SCL       0x527
 | |
| 				ULP1_PAD_PTC5__LPI2C5_SDA       0x527
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC19__PTC19		0x20103
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpuart4: lpuart4grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC3__LPUART4_RX	0x400
 | |
| 				ULP1_PAD_PTC2__LPUART4_TX	0x400
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpuart6: lpuart6grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTE10__LPUART6_TX	0x400
 | |
| 				ULP1_PAD_PTE11__LPUART6_RX	0x400
 | |
| 				ULP1_PAD_PTE9__LPUART6_RTS_B	0x400
 | |
| 				ULP1_PAD_PTE8__LPUART6_CTS_B	0x400
 | |
| 				ULP1_PAD_PTE7__PTE7		0x00 /* BT_REG_ON */
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpuart7: lpuart7grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTF14__LPUART7_TX	0x400
 | |
| 				ULP1_PAD_PTF15__LPUART7_RX	0x400
 | |
| 				ULP1_PAD_PTF13__LPUART7_RTS_B	0x400
 | |
| 				ULP1_PAD_PTF12__LPUART7_CTS_B	0x400
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_usdhc0: usdhc0grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTD1__SDHC0_CMD	0x843
 | |
| 				ULP1_PAD_PTD2__SDHC0_CLK	0x10843
 | |
| 				ULP1_PAD_PTD7__SDHC0_D3		0x843
 | |
| 				ULP1_PAD_PTD8__SDHC0_D2		0x843
 | |
| 				ULP1_PAD_PTD9__SDHC0_D1		0x843
 | |
| 				ULP1_PAD_PTD10__SDHC0_D0	0x843
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_usdhc0_8bit: usdhc0grp_8bit {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTD1__SDHC0_CMD	0x843
 | |
| 				ULP1_PAD_PTD2__SDHC0_CLK	0x843
 | |
| 				ULP1_PAD_PTD3__SDHC0_D7		0x843
 | |
| 				ULP1_PAD_PTD4__SDHC0_D6		0x843
 | |
| 				ULP1_PAD_PTD5__SDHC0_D5		0x843
 | |
| 				ULP1_PAD_PTD6__SDHC0_D4		0x843
 | |
| 				ULP1_PAD_PTD7__SDHC0_D3		0x843
 | |
| 				ULP1_PAD_PTD8__SDHC0_D2		0x843
 | |
| 				ULP1_PAD_PTD9__SDHC0_D1		0x843
 | |
| 				ULP1_PAD_PTD10__SDHC0_D0	0x843
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpi2c7: lpi2c7grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTF12__LPI2C7_SCL	0x527
 | |
| 				ULP1_PAD_PTF13__LPI2C7_SDA	0x527
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_lpspi3: lpspi3grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTF16__LPSPI3_SIN      0x300
 | |
| 				ULP1_PAD_PTF17__LPSPI3_SOUT     0x300
 | |
| 				ULP1_PAD_PTF18__LPSPI3_SCK      0x300
 | |
| 				ULP1_PAD_PTF19__LPSPI3_PCS0     0x300
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_usb_otg1: usbotg1grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC0__PTC0		0x30100
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_extcon_usb1: extcon1grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTC8__PTC8		0x30103
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_usdhc1: usdhc1grp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTE3__SDHC1_CMD	0x843
 | |
| 				ULP1_PAD_PTE2__SDHC1_CLK	0x843
 | |
| 				ULP1_PAD_PTE1__SDHC1_D0		0x843
 | |
| 				ULP1_PAD_PTE0__SDHC1_D1		0x843
 | |
| 				ULP1_PAD_PTE5__SDHC1_D2		0x843
 | |
| 				ULP1_PAD_PTE4__SDHC1_D3		0x843
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_usdhc1_rst: usdhc1grp_rst {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTE11__PTE11			0x30100	/* USDHC1 RST */
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_wifi: wifigrp {
 | |
| 			fsl,pins = <
 | |
| 				ULP1_PAD_PTE6__PTE6		0x43 /* WL_REG_ON */
 | |
| 			>;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &lcdif {
 | |
| 	status = "okay";
 | |
| 	disp-dev = "mipi_dsi_northwest";
 | |
| 	display = <&display0>;
 | |
| 
 | |
| 	display0: display {
 | |
| 		bits-per-pixel = <16>;
 | |
| 		bus-width = <24>;
 | |
| 
 | |
| 		display-timings {
 | |
| 			native-mode = <&timing0>;
 | |
| 			timing0: timing0 {
 | |
| 			clock-frequency = <9200000>;
 | |
| 			hactive = <480>;
 | |
| 			vactive = <272>;
 | |
| 			hfront-porch = <8>;
 | |
| 			hback-porch = <4>;
 | |
| 			hsync-len = <41>;
 | |
| 			vback-porch = <2>;
 | |
| 			vfront-porch = <4>;
 | |
| 			vsync-len = <10>;
 | |
| 
 | |
| 			hsync-active = <0>;
 | |
| 			vsync-active = <0>;
 | |
| 			de-active = <1>;
 | |
| 			pixelclk-active = <0>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &lpi2c7 {
 | |
| 	#address-cells = <1>;
 | |
| 	#size-cells = <0>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpi2c7>;
 | |
| };
 | |
| 
 | |
| &lpi2c5 {
 | |
| 	#address-cells = <1>;
 | |
| 	#size-cells = <0>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpi2c5>;
 | |
| 	status = "okay";
 | |
| 
 | |
| 	fxas2100x@20 {
 | |
| 		compatible = "fsl,fxas2100x";
 | |
| 		reg = <0x20>;
 | |
| 	};
 | |
| 
 | |
| 	fxos8700@1e {
 | |
| 		compatible = "fsl,fxos8700";
 | |
| 		reg = <0x1e>;
 | |
| 	};
 | |
| 
 | |
| 	mpl3115@60 {
 | |
| 		compatible = "fsl,mpl3115";
 | |
| 		reg = <0x60>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &lpspi3 {
 | |
| 	#address-cells = <1>;
 | |
| 	#size-cells = <0>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpspi3>;
 | |
| 	status = "okay";
 | |
| 
 | |
| 	spidev0: spi@0 {
 | |
| 		reg = <0>;
 | |
| 		compatible = "rohm,dh2228fv";
 | |
| 		spi-max-frequency = <1000000>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &mipi_dsi {
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
 | |
| 	lcd_panel = "TRULY-WVGA-TFT3P5581E";
 | |
| 	resets = <&mipi_dsi_reset>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &lpuart4 { /* console */
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpuart4>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &lpuart6 { /* BT */
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpuart6>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &lpuart7 { /* Uart test */
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_lpuart7>;
 | |
| 	status = "disabled";
 | |
| };
 | |
| 
 | |
| &rpmsg{
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &usbotg1 {
 | |
| 	vbus-supply = <®_usb_otg1_vbus>;
 | |
| 	extcon = <0>, <&extcon_usb1>;
 | |
| 	srp-disable;
 | |
| 	hnp-disable;
 | |
| 	adp-disable;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &usdhc0 {
 | |
| 	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 | |
| 	pinctrl-0 = <&pinctrl_usdhc0>;
 | |
| 	pinctrl-1 = <&pinctrl_usdhc0>;
 | |
| 	pinctrl-2 = <&pinctrl_usdhc0>;
 | |
| 	pinctrl-3 = <&pinctrl_usdhc0>;
 | |
| 	cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 | |
| 	vmmc-supply = <®_vsd_3v3>;
 | |
| 	vqmmc-supply = <&vldo2_reg>;
 | |
| 	status = "okay";
 | |
| };
 |