Ley Foon Tan 2b09ea48dd arm: socfpga: Restructure reset manager driver ...

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

2017-05-18 11:33:17 +02:00

..

include/mach

arm: socfpga: Restructure reset manager driver

2017-05-18 11:33:17 +02:00

board.c

arm: socfpga: Introduce common board code

2015-12-20 03:36:51 +01:00

clock_manager_gen5.c

arm: socfpga: Restructure clock manager driver

2017-05-18 11:33:16 +02:00

clock_manager.c

arm: socfpga: Restructure clock manager driver

2017-05-18 11:33:16 +02:00

fpga_manager.c

treewide: replace #include <asm/errno.h> with <linux/errno.h>

2016-09-23 17:55:42 -04:00

freeze_controller.c

treewide: replace #include <asm/errno.h> with <linux/errno.h>

2016-09-23 17:55:42 -04:00

Kconfig

arm: socfpga: add cyclone5 based de10-nano board

2017-04-25 12:46:44 +02:00

Makefile

arm: socfpga: Restructure reset manager driver

2017-05-18 11:33:17 +02:00

misc.c

Fix spelling of "resetting".

2016-10-31 10:13:17 -04:00

qts-filter.sh

qts-filter.sh: strip DOS line endings and handle continuation lines

2016-12-06 01:45:57 +01:00

reset_manager_gen5.c

arm: socfpga: Restructure reset manager driver

2017-05-18 11:33:17 +02:00

reset_manager.c

arm: socfpga: Restructure reset manager driver

2017-05-18 11:33:17 +02:00

scan_manager.c

…

spl.c

arm: socfpga: Restructure clock manager driver

2017-05-18 11:33:16 +02:00

system_manager.c

…

timer.c

…

wrap_iocsr_config.c

…

wrap_pinmux_config.c

…

wrap_pll_config.c

arm: socfpga: set the mpuclk divider in the Altera group register

2017-02-08 02:19:11 +01:00

wrap_sdram_config.c

ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-10-27 08:03:07 +02:00