Philipp Tomsich ba3bf3879e rockchip: clk: rk3399: 24MHz is not a power of 2 ...

The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>

2017-04-04 20:01:57 -06:00

..

aspeed

aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

2017-02-08 15:56:30 -05:00

at91

dm: allow limiting pre-reloc markings to spl or tpl

2017-03-16 16:03:44 -06:00

exynos

…

rockchip

rockchip: clk: rk3399: 24MHz is not a power of 2

2017-04-04 20:01:57 -06:00

tegra

…

uniphier

clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock

2017-01-29 20:59:08 +09:00

clk_boston.c

…

clk_fixed_rate.c

dm: core: Replace of_offset with accessor

2017-02-08 06:12:14 -07:00

clk_pic32.c

dm: core: Replace of_offset with accessor

2017-02-08 06:12:14 -07:00

clk_sandbox_test.c

…

clk_sandbox.c

…

clk_stm32f7.c

stm32f7: clk: remove usart1 clock enable from board init

2017-03-17 14:15:14 -04:00

clk_zynq.c

clk: zynq: Add optional ethernet emio clock source support

2017-02-17 10:22:46 +01:00

clk_zynqmp.c

clk: zynqmp: Add clock driver support for zynqmp

2017-01-10 10:18:12 +01:00

clk-uclass.c

dm: core: Replace of_offset with accessor

2017-02-08 06:12:14 -07:00

Kconfig

clk: zynq: Add zynq clock framework driver

2017-02-17 10:22:46 +01:00

Makefile

clk: stm32f7: add clock driver for stm32f7 family

2017-03-17 14:15:12 -04:00