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u-boot-megous/drivers/clk
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Patrice Chotard 8b41464547 clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock 
On all STM32F4 and F7 SoCs  family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
2018-05-08 09:07:34 -04:00
..
aspeed
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2018-05-07 09:34:12 -04:00
at91
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2018-05-07 09:34:12 -04:00
exynos
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renesas
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2018-05-07 09:34:12 -04:00
rockchip
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tegra
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2018-05-07 09:34:12 -04:00
uniphier
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2018-05-07 09:34:12 -04:00
clk_bcm6345.c
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2018-05-07 09:34:12 -04:00
clk_boston.c
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2018-05-07 09:34:12 -04:00
clk_fixed_rate.c
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2018-05-07 09:34:12 -04:00
clk_pic32.c
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2018-05-07 09:34:12 -04:00
clk_sandbox_test.c
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2018-05-07 09:34:12 -04:00
clk_sandbox.c
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2018-05-07 09:34:12 -04:00
clk_stm32f.c
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
2018-05-08 09:07:34 -04:00
clk_stm32h7.c
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2018-05-07 09:34:12 -04:00
clk_stm32mp1.c
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2018-05-07 10:24:31 -04:00
clk_zynq.c
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2018-05-07 09:34:12 -04:00
clk_zynqmp.c
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2018-05-07 09:34:12 -04:00
clk-hsdk-cgu.c
Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
2018-04-27 14:54:48 -04:00
clk-uclass.c
SPDX: Convert all of our single license tags to Linux Kernel style
2018-05-07 09:34:12 -04:00
Kconfig
clk: add driver for stm32mp1
2018-03-19 16:14:22 -04:00
Makefile
clk: add driver for stm32mp1
2018-03-19 16:14:22 -04:00