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4684a7a43a
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
354 lines
8.6 KiB
C
354 lines
8.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __NIX_H__
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#define __NIX_H__
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#include <asm/arch/csrs/csrs-npa.h>
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#include <asm/arch/csrs/csrs-nix.h>
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#include "rvu.h"
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/** Maximum number of LMACs supported */
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#define MAX_LMAC 12
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/* NIX RX action operation*/
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#define NIX_RX_ACTIONOP_DROP (0x0ull)
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#define NIX_RX_ACTIONOP_UCAST (0x1ull)
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#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
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#define NIX_RX_ACTIONOP_MCAST (0x3ull)
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#define NIX_RX_ACTIONOP_RSS (0x4ull)
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/* NIX TX action operation*/
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#define NIX_TX_ACTIONOP_DROP (0x0ull)
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#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
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#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
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#define NIX_TX_ACTIONOP_MCAST (0x3ull)
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#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
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#define NIX_INTF_RX 0
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#define NIX_INTF_TX 1
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#define NIX_INTF_TYPE_CGX 0
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#define NIX_INTF_TYPE_LBK 1
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#define NIX_MAX_HW_MTU 9212
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#define NIX_MIN_HW_MTU 40
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#define MAX_MTU 1536
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#define NPA_POOL_COUNT 3
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#define NPA_AURA_COUNT(x) (1ULL << ((x) + 6))
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#define NPA_POOL_RX 0ULL
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#define NPA_POOL_TX 1ULL
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#define NPA_POOL_SQB 2ULL
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#define RQ_QLEN Q_COUNT(Q_SIZE_1K)
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#define SQ_QLEN Q_COUNT(Q_SIZE_1K)
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#define SQB_QLEN Q_COUNT(Q_SIZE_16)
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#define NIX_CQ_RX 0ULL
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#define NIX_CQ_TX 1ULL
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#define NIX_CQ_COUNT 2ULL
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#define NIX_CQE_SIZE_W16 (16 * sizeof(u64))
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#define NIX_CQE_SIZE_W64 (64 * sizeof(u64))
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/** Size of aura hardware context */
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#define NPA_AURA_HW_CTX_SIZE 48
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/** Size of pool hardware context */
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#define NPA_POOL_HW_CTX_SIZE 64
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#define NPA_DEFAULT_PF_FUNC 0xffff
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#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
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#define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
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#define NIX_LINK_LBK(a) (12 + (a))
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#define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b))
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#define MAX_LMAC_PKIND 12
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/** Number of Admin queue entries */
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#define AQ_RING_SIZE Q_COUNT(Q_SIZE_16)
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/** Each completion queue contains 256 entries, see NIC_CQ_CTX_S[qsize] */
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#define CQS_QSIZE Q_SIZE_256
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#define CQ_ENTRIES Q_COUNT(CQS_QSIZE)
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/**
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* Each completion queue entry contains 128 bytes, see
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* NIXX_AF_LFX_CFG[xqe_size]
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*/
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#define CQ_ENTRY_SIZE NIX_CQE_SIZE_W16
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enum npa_aura_size {
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NPA_AURA_SZ_0,
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NPA_AURA_SZ_128,
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NPA_AURA_SZ_256,
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NPA_AURA_SZ_512,
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NPA_AURA_SZ_1K,
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NPA_AURA_SZ_2K,
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NPA_AURA_SZ_4K,
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NPA_AURA_SZ_8K,
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NPA_AURA_SZ_16K,
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NPA_AURA_SZ_32K,
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NPA_AURA_SZ_64K,
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NPA_AURA_SZ_128K,
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NPA_AURA_SZ_256K,
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NPA_AURA_SZ_512K,
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NPA_AURA_SZ_1M,
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NPA_AURA_SZ_MAX,
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};
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#define NPA_AURA_SIZE_DEFAULT NPA_AURA_SZ_128
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/* NIX Transmit schedulers */
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enum nix_scheduler {
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NIX_TXSCH_LVL_SMQ = 0x0,
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NIX_TXSCH_LVL_MDQ = 0x0,
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NIX_TXSCH_LVL_TL4 = 0x1,
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NIX_TXSCH_LVL_TL3 = 0x2,
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NIX_TXSCH_LVL_TL2 = 0x3,
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NIX_TXSCH_LVL_TL1 = 0x4,
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NIX_TXSCH_LVL_CNT = 0x5,
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};
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struct cgx;
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struct nix_stats {
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u64 num_packets;
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u64 num_bytes;
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};
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struct nix;
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struct lmac;
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struct npa_af {
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void __iomem *npa_af_base;
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struct admin_queue aq;
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u32 aura;
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};
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struct npa {
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struct npa_af *npa_af;
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void __iomem *npa_base;
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void __iomem *npc_base;
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void __iomem *lmt_base;
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/** Hardware aura context */
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void *aura_ctx;
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/** Hardware pool context */
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void *pool_ctx[NPA_POOL_COUNT];
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void *pool_stack[NPA_POOL_COUNT];
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void **buffers[NPA_POOL_COUNT];
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u32 pool_stack_pages[NPA_POOL_COUNT];
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u32 pool_stack_pointers;
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u32 q_len[NPA_POOL_COUNT];
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u32 buf_size[NPA_POOL_COUNT];
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u32 stack_pages[NPA_POOL_COUNT];
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};
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struct nix_af {
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struct udevice *dev;
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struct nix *lmacs[MAX_LMAC];
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struct npa_af *npa_af;
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void __iomem *nix_af_base;
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void __iomem *npc_af_base;
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struct admin_queue aq;
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u8 num_lmacs;
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s8 index;
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u8 xqe_size;
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u32 sqb_size;
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u32 qints;
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u32 cints;
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u32 sq_ctx_sz;
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u32 rq_ctx_sz;
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u32 cq_ctx_sz;
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u32 rsse_ctx_sz;
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u32 cint_ctx_sz;
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u32 qint_ctx_sz;
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};
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struct nix_tx_dr {
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union nix_send_hdr_s hdr;
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union nix_send_sg_s tx_sg;
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dma_addr_t sg1_addr;
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dma_addr_t sg2_addr;
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dma_addr_t sg3_addr;
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u64 in_use;
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};
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struct nix_rx_dr {
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union nix_cqe_hdr_s hdr;
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union nix_rx_parse_s rx_parse;
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union nix_rx_sg_s rx_sg;
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};
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struct nix {
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struct udevice *dev;
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struct eth_device *netdev;
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struct nix_af *nix_af;
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struct npa *npa;
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struct lmac *lmac;
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union nix_cint_hw_s *cint_base;
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union nix_cq_ctx_s *cq_ctx_base;
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union nix_qint_hw_s *qint_base;
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union nix_rq_ctx_s *rq_ctx_base;
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union nix_rsse_s *rss_base;
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union nix_sq_ctx_s *sq_ctx_base;
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void *cqe_base;
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struct qmem sq;
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struct qmem cq[NIX_CQ_COUNT];
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struct qmem rq;
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struct qmem rss;
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struct qmem cq_ints;
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struct qmem qints;
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char name[16];
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void __iomem *nix_base; /** PF reg base */
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void __iomem *npc_base;
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void __iomem *lmt_base;
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struct nix_stats tx_stats;
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struct nix_stats rx_stats;
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u32 aura;
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int pknd;
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int lf;
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int pf;
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u16 pf_func;
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u32 rq_cnt; /** receive queues count */
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u32 sq_cnt; /** send queues count */
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u32 cq_cnt; /** completion queues count */
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u16 rss_sz;
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u16 sqb_size;
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u8 rss_grps;
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u8 xqe_sz;
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};
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struct nix_aq_cq_dis {
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union nix_aq_res_s resp ALIGNED;
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union nix_cq_ctx_s cq ALIGNED;
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union nix_cq_ctx_s mcq ALIGNED;
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};
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struct nix_aq_rq_dis {
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union nix_aq_res_s resp ALIGNED;
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union nix_rq_ctx_s rq ALIGNED;
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union nix_rq_ctx_s mrq ALIGNED;
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};
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struct nix_aq_sq_dis {
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union nix_aq_res_s resp ALIGNED;
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union nix_sq_ctx_s sq ALIGNED;
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union nix_sq_ctx_s msq ALIGNED;
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};
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struct nix_aq_cq_request {
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union nix_aq_res_s resp ALIGNED;
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union nix_cq_ctx_s cq ALIGNED;
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};
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struct nix_aq_rq_request {
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union nix_aq_res_s resp ALIGNED;
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union nix_rq_ctx_s rq ALIGNED;
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};
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struct nix_aq_sq_request {
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union nix_aq_res_s resp ALIGNED;
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union nix_sq_ctx_s sq ALIGNED;
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};
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static inline u64 nix_af_reg_read(struct nix_af *nix_af, u64 offset)
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{
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u64 val = readq(nix_af->nix_af_base + offset);
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debug("%s reg %p val %llx\n", __func__, nix_af->nix_af_base + offset,
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val);
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return val;
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}
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static inline void nix_af_reg_write(struct nix_af *nix_af, u64 offset,
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u64 val)
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{
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debug("%s reg %p val %llx\n", __func__, nix_af->nix_af_base + offset,
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val);
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writeq(val, nix_af->nix_af_base + offset);
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}
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static inline u64 nix_pf_reg_read(struct nix *nix, u64 offset)
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{
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u64 val = readq(nix->nix_base + offset);
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debug("%s reg %p val %llx\n", __func__, nix->nix_base + offset,
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val);
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return val;
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}
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static inline void nix_pf_reg_write(struct nix *nix, u64 offset,
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u64 val)
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{
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debug("%s reg %p val %llx\n", __func__, nix->nix_base + offset,
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val);
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writeq(val, nix->nix_base + offset);
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}
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static inline u64 npa_af_reg_read(struct npa_af *npa_af, u64 offset)
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{
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u64 val = readq(npa_af->npa_af_base + offset);
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debug("%s reg %p val %llx\n", __func__, npa_af->npa_af_base + offset,
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val);
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return val;
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}
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static inline void npa_af_reg_write(struct npa_af *npa_af, u64 offset,
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u64 val)
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{
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debug("%s reg %p val %llx\n", __func__, npa_af->npa_af_base + offset,
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val);
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writeq(val, npa_af->npa_af_base + offset);
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}
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static inline u64 npc_af_reg_read(struct nix_af *nix_af, u64 offset)
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{
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u64 val = readq(nix_af->npc_af_base + offset);
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debug("%s reg %p val %llx\n", __func__, nix_af->npc_af_base + offset,
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val);
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return val;
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}
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static inline void npc_af_reg_write(struct nix_af *nix_af, u64 offset,
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u64 val)
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{
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debug("%s reg %p val %llx\n", __func__, nix_af->npc_af_base + offset,
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val);
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writeq(val, nix_af->npc_af_base + offset);
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}
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int npa_attach_aura(struct nix_af *nix_af, int lf,
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const union npa_aura_s *desc, u32 aura_id);
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int npa_attach_pool(struct nix_af *nix_af, int lf,
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const union npa_pool_s *desc, u32 pool_id);
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int npa_af_setup(struct npa_af *npa_af);
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int npa_af_shutdown(struct npa_af *npa_af);
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int npa_lf_setup(struct nix *nix);
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int npa_lf_shutdown(struct nix *nix);
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int npa_lf_admin_setup(struct npa *npa, int lf, dma_addr_t aura_base);
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int npa_lf_admin_shutdown(struct nix_af *nix_af, int lf, u32 pool_count);
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int npc_lf_admin_setup(struct nix *nix);
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int npc_af_shutdown(struct nix_af *nix_af);
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int nix_af_setup(struct nix_af *nix_af);
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int nix_af_shutdown(struct nix_af *nix_af);
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int nix_lf_setup(struct nix *nix);
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int nix_lf_shutdown(struct nix *nix);
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struct nix *nix_lf_alloc(struct udevice *dev);
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int nix_lf_admin_setup(struct nix *nix);
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int nix_lf_admin_shutdown(struct nix_af *nix_af, int lf,
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u32 cq_count, u32 rq_count, u32 sq_count);
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struct rvu_af *get_af(void);
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int nix_lf_setup_mac(struct udevice *dev);
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int nix_lf_read_rom_mac(struct udevice *dev);
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void nix_lf_halt(struct udevice *dev);
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int nix_lf_free_pkt(struct udevice *dev, uchar *pkt, int pkt_len);
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int nix_lf_recv(struct udevice *dev, int flags, uchar **packetp);
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int nix_lf_init(struct udevice *dev);
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int nix_lf_xmit(struct udevice *dev, void *pkt, int pkt_len);
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#endif /* __NIX_H__ */
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