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00160cf32e
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.
Fixes: 5a78a472f6 ("armv8/ls1043a: RGMII PHY requires internal
delay on Tx")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
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#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
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#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
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#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
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#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
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#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
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#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
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#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
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#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
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[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
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[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
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[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
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[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
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[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
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[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
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[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
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[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
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};
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static int is_device_disabled(enum fm_port port)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
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return PHY_INTERFACE_MODE_XGMII;
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if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
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return PHY_INTERFACE_MODE_NONE;
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if (port == FM1_DTSEC3)
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
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FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
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return PHY_INTERFACE_MODE_RGMII_ID;
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}
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if (port == FM1_DTSEC4)
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if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
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FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
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return PHY_INTERFACE_MODE_RGMII_ID;
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}
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/* handle SGMII */
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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if ((port == FM1_DTSEC2) &&
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is_serdes_configured(SGMII_2500_FM1_DTSEC2))
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return PHY_INTERFACE_MODE_SGMII_2500;
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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case FM1_DTSEC9:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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else if ((port == FM1_DTSEC9) &&
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is_serdes_configured(SGMII_2500_FM1_DTSEC9))
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return PHY_INTERFACE_MODE_SGMII_2500;
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break;
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default:
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break;
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}
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/* handle QSGMII */
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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/* only MAC 1,2,5,6 available for QSGMII */
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if (is_serdes_configured(QSGMII_FM1_A))
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return PHY_INTERFACE_MODE_QSGMII;
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break;
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default:
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break;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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