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	Introduce STM32MP2 SoCs family support Add STM32MP257F-EV1 board [trini: Adjust some includes] Signed-off-by: Tom Rini <trini@konsulko.com>
		
			
				
	
	
		
			69 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			69 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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| /*
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|  * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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|  */
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| 
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| #include <asm/system.h>
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| #include <asm/armv8/mmu.h>
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| #include <mach/stm32.h>
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| 
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| #define MP2_MEM_MAP_MAX 10
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| 
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| #if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
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| 	(CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
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| #error "invalid CONFIG_TEXT_BASE value"
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| #endif
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| 
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| struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
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| 	{
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| 		/* PCIe */
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| 		.virt = 0x10000000UL,
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| 		.phys = 0x10000000UL,
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| 		.size = 0x10000000UL,
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| 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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| 			 PTE_BLOCK_NON_SHARE |
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| 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
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| 	}, {
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| 		/* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
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| 		.virt = 0x20000000UL,
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| 		.phys = 0x20000000UL,
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| 		.size = 0x00200000UL,
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| 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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| 			 PTE_BLOCK_NON_SHARE |
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| 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
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| 	}, {
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| 		/* Peripherals: alias1 */
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| 		.virt = 0x40000000UL,
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| 		.phys = 0x40000000UL,
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| 		.size = 0x10000000UL,
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| 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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| 			 PTE_BLOCK_NON_SHARE |
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| 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
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| 	}, {
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| 		/* OSPI and FMC: memory-map area */
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| 		.virt = 0x60000000UL,
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| 		.phys = 0x60000000UL,
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| 		.size = 0x20000000UL,
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| 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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| 			 PTE_BLOCK_NON_SHARE |
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| 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
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| 	}, {
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| 		/*
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| 		 * DDR = STM32_DDR_BASE / STM32_DDR_SIZE
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| 		 * the beginning of DDR (before CONFIG_TEXT_BASE) is not
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| 		 * mapped, protected by RIF and reserved for other firmware
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| 		 * (OP-TEE / TF-M / Cube M33)
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| 		 */
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| 		.virt = CONFIG_TEXT_BASE,
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| 		.phys = CONFIG_TEXT_BASE,
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| 		.size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
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| 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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| 			 PTE_BLOCK_INNER_SHARE
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| 	}, {
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| 		/* List terminator */
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| 		0,
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| 	}
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| };
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| 
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| struct mm_region *mem_map = stm32mp2_mem_map;
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