mirror of
https://xff.cz/git/u-boot/
synced 2025-10-31 18:35:42 +01:00
54a08c4139
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR4_MPR_PDA_IF_H
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#define _MV_DDR4_MPR_PDA_IF_H
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#include "ddr3_init.h"
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#include "mv_ddr_common.h"
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#define MV_DDR4_VREF_STEP_SIZE 3
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#define MV_DDR4_VREF_MIN_RANGE 1
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#define MV_DDR4_VREF_MAX_RANGE 73
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#define MV_DDR4_VREF_MAX_COUNT (((MV_DDR4_VREF_MAX_RANGE - MV_DDR4_VREF_MIN_RANGE) / MV_DDR4_VREF_STEP_SIZE) + 2)
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#define MV_DDR4_MPR_READ_PATTERN_NUM 3
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enum mv_ddr4_mpr_read_format {
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MV_DDR4_MPR_READ_SERIAL,
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MV_DDR4_MPR_READ_PARALLEL,
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MV_DDR4_MPR_READ_STAGGERED,
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MV_DDR4_MPR_READ_RSVD_TEMP
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};
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enum mv_ddr4_mpr_read_type {
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MV_DDR4_MPR_READ_RAW,
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MV_DDR4_MPR_READ_DECODED
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};
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enum mv_ddr4_vref_tap_state {
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MV_DDR4_VREF_TAP_START,
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MV_DDR4_VREF_TAP_BUSY,
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MV_DDR4_VREF_TAP_FLIP,
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MV_DDR4_VREF_TAP_END
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};
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int mv_ddr4_mode_regs_init(u8 dev_num);
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int mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num,
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enum mv_ddr4_mpr_read_format read_format,
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enum mv_ddr4_mpr_read_type read_type,
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u32 *data);
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int mv_ddr4_mpr_write(u8 dev_num, u32 mpr_location, u32 mpr_num,
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u32 page_num, u32 data);
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int mv_ddr4_dq_pins_mapping(u8 dev_num);
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int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id,
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enum hws_access_type access_type,
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int enable);
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int mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id,
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enum hws_access_type access_type,
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u32 taps_num,
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enum mv_ddr4_vref_tap_state state);
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int mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type,
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u32 range, u32 vdq_tv, u8 vdq_training_ena);
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int mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type,
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u32 if_id, u32 subphy_mask, u32 cs_num);
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int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
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#endif /* _MV_DDR4_MPR_PDA_IF_H */
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