Tien Fong Chee 4ae87a83a6 arm: socfpga: Fix with the correct polling on bit is set ...

Commit 2baa997240 ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.

Fixes: 2baa997240 ("arm: socfpga: Add FPGA driver support for Arria 10")

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

2018-04-27 01:04:08 +02:00

..

ACEX1K.c

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altera.c

fpga: altera: Add StratixV support

2016-03-24 09:47:43 +01:00

cyclon2.c

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fpga.c

fpga: Simplify error path in fpga_add

2018-03-23 09:34:42 +01:00

ivm_core.c

FPGA: drivers/fpga/ivm_core.c: incorrect printf

2017-04-18 10:29:23 -04:00

Kconfig

arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL

2018-02-28 13:00:25 -05:00

lattice.c

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Makefile

arm: socfpga: Add FPGA driver support for Arria 10

2017-07-26 10:31:44 +02:00

socfpga_arria10.c

arm: socfpga: Fix with the correct polling on bit is set

2018-04-27 01:04:08 +02:00

socfpga_gen5.c

arm: socfpga: Restructure FPGA driver in the preparation to support A10

2017-07-26 10:31:44 +02:00

socfpga.c

arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes

2017-11-26 02:34:10 +01:00

spartan2.c

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spartan3.c

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stratixII.c

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stratixv.c

treewide: replace #include <asm/errno.h> with <linux/errno.h>

2016-09-23 17:55:42 -04:00

virtex2.c

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xilinx.c

fpga: allow programming fpga from FIT image for all FPGA drivers

2017-12-14 16:09:39 +01:00

zynqmppl.c

fpga: zynqmp: Fix the nonsecure bitstream loading issue

2018-04-09 12:14:50 +02:00

zynqpl.c

fpga: zynq: Add delay after PCFG_PROG_B change

2018-04-09 12:14:50 +02:00