Chris Packham 3cb51dad0d net: phy: mv88e61xx: Force CPU port link up ...

When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

2018-06-13 13:54:17 -05:00

..

aquantia.c

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2018-05-07 09:34:12 -04:00

atheros.c

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2018-05-07 09:34:12 -04:00

b53.c

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2018-05-07 09:34:12 -04:00

broadcom.c

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2018-05-07 09:34:12 -04:00

cortina.c

net/phy/cortina: Add support for CS4223 PHY

2018-06-13 13:54:15 -05:00

davicom.c

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2018-05-07 09:34:12 -04:00

et1011c.c

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2018-05-07 09:34:12 -04:00

fixed.c

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2018-05-07 09:34:12 -04:00

generic_10g.c

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2018-05-07 09:34:12 -04:00

Kconfig

net: phy: Don't limit phy addresses by default

2018-04-13 15:56:47 -05:00

lxt.c

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2018-05-07 09:34:12 -04:00

Makefile

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marvell.c

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2018-05-07 09:34:12 -04:00

meson-gxl.c

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2018-05-07 09:34:12 -04:00

micrel_ksz8xxx.c

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2018-05-07 09:34:12 -04:00

micrel_ksz90x1.c

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2018-05-07 09:34:12 -04:00

miiphybb.c

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2018-05-07 09:34:12 -04:00

mscc.c

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2018-05-07 09:34:12 -04:00

mv88e61xx.c

net: phy: mv88e61xx: Force CPU port link up

2018-06-13 13:54:17 -05:00

mv88e6352.c

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2018-05-07 09:34:12 -04:00

natsemi.c

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2018-05-07 09:34:12 -04:00

phy.c

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2018-05-07 09:34:12 -04:00

realtek.c

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2018-05-07 09:34:12 -04:00

smsc.c

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2018-05-07 09:34:12 -04:00

teranetics.c

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ti.c

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2018-05-07 09:34:12 -04:00

vitesse.c

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2018-05-07 09:34:12 -04:00

xilinx_phy.c

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2018-05-07 09:34:12 -04:00