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The NAND framework makes sure to pass in the buffer with at least chip->buf_align alignment. Currently, the Denali NAND driver only requests 16 byte alignment. This causes unaligned cache operations for the DMA transfer. [Error Example] => nand read 81000010 0 1000 NAND read: device 0 offset 0x0, size 0x1000 CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] 4096 bytes read: OK Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>