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12308b128f
This patch renames the routine fdtdec_setup_memory_size() to fdtdec_setup_mem_size_base() as it now fills the mem base as well along with size. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
111 lines
2.6 KiB
C
111 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/ulcb/ulcb.c
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* This file is ULCB board support.
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPCR 0xE6150904
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#define CPGWPR 0xE615090C
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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writel(0xA5A50000, CPGWPCR);
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writel(0xFFFFFFFF, CPGWPR);
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}
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#define GSX_MSTP112 BIT(12) /* 3DG */
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#define TMU0_MSTP125 BIT(25) /* secure */
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#define TMU1_MSTP124 BIT(24) /* non-secure */
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
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#define DVFS_MSTP926 BIT(26)
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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int board_early_init_f(void)
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{
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/* TMU0,1 */ /* which use ? */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
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/* DVFS for reset */
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
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#endif
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return 0;
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}
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/* SYSC */
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/* R/- 32 Power status register 2(3DG) */
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#define SYSC_PWRSR2 0xE6180100
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/* -/W 32 Power resume control register 2 (3DG) */
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#define SYSC_PWRONCR2 0xE618010C
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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/* USB1 pull-up */
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
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/* Configure the HSUSB block */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
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/* Choice USB0SEL */
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clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
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HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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