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06142d6874
The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
197 lines
7.4 KiB
C
197 lines
7.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
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#define PLIC_INT_INVALID 0
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#define PLIC_INT_L2_METADATA_CORR 1
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#define PLIC_INT_L2_METADATA_UNCORR 2
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#define PLIC_INT_L2_DATA_CORR 3
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#define PLIC_INT_L2_DATA_UNCORR 4
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#define PLIC_INT_DMA_CH0_DONE 5
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#define PLIC_INT_DMA_CH0_ERR 6
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#define PLIC_INT_DMA_CH1_DONE 7
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#define PLIC_INT_DMA_CH1_ERR 8
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#define PLIC_INT_DMA_CH2_DONE 9
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#define PLIC_INT_DMA_CH2_ERR 10
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#define PLIC_INT_DMA_CH3_DONE 11
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#define PLIC_INT_DMA_CH3_ERR 12
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#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13
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#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14
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#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15
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#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16
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#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17
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#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18
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#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19
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#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20
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#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21
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#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22
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#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23
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#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24
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#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25
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#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26
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#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27
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#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28
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#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29
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#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30
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#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31
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#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32
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#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33
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#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34
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#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35
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#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36
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#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37
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#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38
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#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39
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#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40
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#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41
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#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42
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#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43
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#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44
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#define PLIC_INT_GPIO1_BIT18 45
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#define PLIC_INT_GPIO1_BIT19 46
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#define PLIC_INT_GPIO1_BIT20 47
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#define PLIC_INT_GPIO1_BIT21 48
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#define PLIC_INT_GPIO1_BIT22 49
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#define PLIC_INT_GPIO1_BIT23 50
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#define PLIC_INT_GPIO0_NON_DIRECT 51
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#define PLIC_INT_GPIO1_NON_DIRECT 52
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#define PLIC_INT_GPIO2_NON_DIRECT 53
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#define PLIC_INT_SPI0 54
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#define PLIC_INT_SPI1 55
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#define PLIC_INT_CAN0 56
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#define PLIC_INT_CAN1 57
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#define PLIC_INT_I2C0_MAIN 58
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#define PLIC_INT_I2C0_ALERT 59
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#define PLIC_INT_I2C0_SUS 60
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#define PLIC_INT_I2C1_MAIN 61
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#define PLIC_INT_I2C1_ALERT 62
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#define PLIC_INT_I2C1_SUS 63
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#define PLIC_INT_MAC0_INT 64
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#define PLIC_INT_MAC0_QUEUE1 65
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#define PLIC_INT_MAC0_QUEUE2 66
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#define PLIC_INT_MAC0_QUEUE3 67
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#define PLIC_INT_MAC0_EMAC 68
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#define PLIC_INT_MAC0_MMSL 69
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#define PLIC_INT_MAC1_INT 70
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#define PLIC_INT_MAC1_QUEUE1 71
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#define PLIC_INT_MAC1_QUEUE2 72
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#define PLIC_INT_MAC1_QUEUE3 73
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#define PLIC_INT_MAC1_EMAC 74
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#define PLIC_INT_MAC1_MMSL 75
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#define PLIC_INT_DDRC_TRAIN 76
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#define PLIC_INT_SCB_INTERRUPT 77
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#define PLIC_INT_ECC_ERROR 78
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#define PLIC_INT_ECC_CORRECT 79
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#define PLIC_INT_RTC_WAKEUP 80
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#define PLIC_INT_RTC_MATCH 81
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#define PLIC_INT_TIMER1 82
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#define PLIC_INT_TIMER2 83
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#define PLIC_INT_ENVM 84
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#define PLIC_INT_QSPI 85
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#define PLIC_INT_USB_DMA 86
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#define PLIC_INT_USB_MC 87
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#define PLIC_INT_MMC_MAIN 88
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#define PLIC_INT_MMC_WAKEUP 89
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#define PLIC_INT_MMUART0 90
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#define PLIC_INT_MMUART1 91
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#define PLIC_INT_MMUART2 92
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#define PLIC_INT_MMUART3 93
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#define PLIC_INT_MMUART4 94
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#define PLIC_INT_G5C_DEVRST 95
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#define PLIC_INT_G5C_MESSAGE 96
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#define PLIC_INT_USOC_VC_INTERRUPT 97
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#define PLIC_INT_USOC_SMB_INTERRUPT 98
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#define PLIC_INT_E51_0_MAINTENACE 99
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#define PLIC_INT_WDOG0_MRVP 100
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#define PLIC_INT_WDOG1_MRVP 101
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#define PLIC_INT_WDOG2_MRVP 102
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#define PLIC_INT_WDOG3_MRVP 103
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#define PLIC_INT_WDOG4_MRVP 104
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#define PLIC_INT_WDOG0_TOUT 105
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#define PLIC_INT_WDOG1_TOUT 106
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#define PLIC_INT_WDOG2_TOUT 107
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#define PLIC_INT_WDOG3_TOUT 108
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#define PLIC_INT_WDOG4_TOUT 109
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#define PLIC_INT_G5C_MSS_SPI 110
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#define PLIC_INT_VOLT_TEMP_ALARM 111
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#define PLIC_INT_ATHENA_COMPLETE 112
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#define PLIC_INT_ATHENA_ALARM 113
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#define PLIC_INT_ATHENA_BUS_ERROR 114
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#define PLIC_INT_USOC_AXIC_US 115
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#define PLIC_INT_USOC_AXIC_DS 116
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#define PLIC_INT_SPARE 117
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#define PLIC_INT_FABRIC_F2H_0 118
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#define PLIC_INT_FABRIC_F2H_1 119
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#define PLIC_INT_FABRIC_F2H_2 120
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#define PLIC_INT_FABRIC_F2H_3 121
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#define PLIC_INT_FABRIC_F2H_4 122
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#define PLIC_INT_FABRIC_F2H_5 123
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#define PLIC_INT_FABRIC_F2H_6 124
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#define PLIC_INT_FABRIC_F2H_7 125
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#define PLIC_INT_FABRIC_F2H_8 126
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#define PLIC_INT_FABRIC_F2H_9 127
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#define PLIC_INT_FABRIC_F2H_10 128
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#define PLIC_INT_FABRIC_F2H_11 129
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#define PLIC_INT_FABRIC_F2H_12 130
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#define PLIC_INT_FABRIC_F2H_13 131
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#define PLIC_INT_FABRIC_F2H_14 132
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#define PLIC_INT_FABRIC_F2H_15 133
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#define PLIC_INT_FABRIC_F2H_16 134
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#define PLIC_INT_FABRIC_F2H_17 135
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#define PLIC_INT_FABRIC_F2H_18 136
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#define PLIC_INT_FABRIC_F2H_19 137
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#define PLIC_INT_FABRIC_F2H_20 138
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#define PLIC_INT_FABRIC_F2H_21 139
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#define PLIC_INT_FABRIC_F2H_22 140
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#define PLIC_INT_FABRIC_F2H_23 141
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#define PLIC_INT_FABRIC_F2H_24 142
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#define PLIC_INT_FABRIC_F2H_25 143
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#define PLIC_INT_FABRIC_F2H_26 144
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#define PLIC_INT_FABRIC_F2H_27 145
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#define PLIC_INT_FABRIC_F2H_28 146
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#define PLIC_INT_FABRIC_F2H_29 147
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#define PLIC_INT_FABRIC_F2H_30 148
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#define PLIC_INT_FABRIC_F2H_31 149
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#define PLIC_INT_FABRIC_F2H_32 150
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#define PLIC_INT_FABRIC_F2H_33 151
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#define PLIC_INT_FABRIC_F2H_34 152
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#define PLIC_INT_FABRIC_F2H_35 153
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#define PLIC_INT_FABRIC_F2H_36 154
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#define PLIC_INT_FABRIC_F2H_37 155
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#define PLIC_INT_FABRIC_F2H_38 156
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#define PLIC_INT_FABRIC_F2H_39 157
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#define PLIC_INT_FABRIC_F2H_40 158
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#define PLIC_INT_FABRIC_F2H_41 159
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#define PLIC_INT_FABRIC_F2H_42 160
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#define PLIC_INT_FABRIC_F2H_43 161
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#define PLIC_INT_FABRIC_F2H_44 162
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#define PLIC_INT_FABRIC_F2H_45 163
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#define PLIC_INT_FABRIC_F2H_46 164
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#define PLIC_INT_FABRIC_F2H_47 165
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#define PLIC_INT_FABRIC_F2H_48 166
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#define PLIC_INT_FABRIC_F2H_49 167
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#define PLIC_INT_FABRIC_F2H_50 168
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#define PLIC_INT_FABRIC_F2H_51 169
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#define PLIC_INT_FABRIC_F2H_52 170
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#define PLIC_INT_FABRIC_F2H_53 171
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#define PLIC_INT_FABRIC_F2H_54 172
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#define PLIC_INT_FABRIC_F2H_55 173
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#define PLIC_INT_FABRIC_F2H_56 174
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#define PLIC_INT_FABRIC_F2H_57 175
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#define PLIC_INT_FABRIC_F2H_58 176
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#define PLIC_INT_FABRIC_F2H_59 177
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#define PLIC_INT_FABRIC_F2H_60 178
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#define PLIC_INT_FABRIC_F2H_61 179
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#define PLIC_INT_FABRIC_F2H_62 180
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#define PLIC_INT_FABRIC_F2H_63 181
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#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182
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#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183
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#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184
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#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185
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#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186
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#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
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