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	Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
		
			
				
	
	
		
			79 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			79 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2010
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|  * Texas Instruments, <www.ti.com>
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|  * Aneesh V <aneesh@ti.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| #ifndef _PL310_H_
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| #define _PL310_H_
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| 
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| #include <linux/types.h>
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| 
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| /* Register bit fields */
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| #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
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| #define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
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| #define L2X0_STNDBY_MODE_EN			(1 << 0)
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| #define L2X0_CTRL_EN				1
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| 
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| struct pl310_regs {
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| 	u32 pl310_cache_id;
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| 	u32 pl310_cache_type;
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| 	u32 pad1[62];
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| 	u32 pl310_ctrl;
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| 	u32 pl310_aux_ctrl;
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| 	u32 pl310_tag_latency_ctrl;
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| 	u32 pl310_data_latency_ctrl;
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| 	u32 pad2[60];
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| 	u32 pl310_event_cnt_ctrl;
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| 	u32 pl310_event_cnt1_cfg;
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| 	u32 pl310_event_cnt0_cfg;
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| 	u32 pl310_event_cnt1_val;
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| 	u32 pl310_event_cnt0_val;
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| 	u32 pl310_intr_mask;
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| 	u32 pl310_masked_intr_stat;
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| 	u32 pl310_raw_intr_stat;
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| 	u32 pl310_intr_clear;
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| 	u32 pad3[323];
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| 	u32 pl310_cache_sync;
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| 	u32 pad4[15];
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| 	u32 pl310_inv_line_pa;
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| 	u32 pad5[2];
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| 	u32 pl310_inv_way;
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| 	u32 pad6[12];
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| 	u32 pl310_clean_line_pa;
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| 	u32 pad7[1];
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| 	u32 pl310_clean_line_idx;
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| 	u32 pl310_clean_way;
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| 	u32 pad8[12];
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| 	u32 pl310_clean_inv_line_pa;
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| 	u32 pad9[1];
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| 	u32 pl310_clean_inv_line_idx;
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| 	u32 pl310_clean_inv_way;
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| 	u32 pad10[64];
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| 	u32 pl310_lockdown_dbase;
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| 	u32 pl310_lockdown_ibase;
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| 	u32 pad11[190];
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| 	u32 pl310_addr_filter_start;
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| 	u32 pl310_addr_filter_end;
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| 	u32 pad12[190];
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| 	u32 pl310_test_operation;
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| 	u32 pad13[3];
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| 	u32 pl310_line_data;
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| 	u32 pad14[7];
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| 	u32 pl310_line_tag;
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| 	u32 pad15[3];
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| 	u32 pl310_debug_ctrl;
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| 	u32 pad16[7];
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| 	u32 pl310_prefetch_ctrl;
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| 	u32 pad17[7];
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| 	u32 pl310_power_ctrl;
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| };
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| 
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| void pl310_inval_all(void);
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| void pl310_clean_inval_all(void);
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| void pl310_inval_range(u32 start, u32 end);
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| void pl310_clean_inval_range(u32 start, u32 end);
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| 
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| #endif
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