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McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
527 lines
14 KiB
C
527 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
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* Christophe Ricard <christophe.ricard@gmail.com>
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <omap3_spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct omap2_mcspi_platform_config {
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unsigned int regs_offset;
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};
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struct omap3_spi_priv {
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struct mcspi *regs;
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unsigned int cs;
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unsigned int freq;
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unsigned int mode;
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unsigned int wordlen;
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unsigned int pin_dir:1;
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bool bus_claimed;
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};
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static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
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{
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writel(val, &priv->regs->channel[priv->cs].chconf);
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/* Flash post writes to make immediate effect */
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readl(&priv->regs->channel[priv->cs].chconf);
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}
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static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
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{
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writel(enable, &priv->regs->channel[priv->cs].chctrl);
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/* Flash post writes to make immediate effect */
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readl(&priv->regs->channel[priv->cs].chctrl);
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}
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static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
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const void *txp, unsigned long flags)
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{
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ulong start;
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int i, chconf;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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for (i = 0; i < len; i++) {
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/* wait till TX register is empty (TXS == 1) */
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &priv->regs->channel[priv->cs].tx;
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if (priv->wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (priv->wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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}
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/* wait to finish of transfer */
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while ((readl(&priv->regs->channel[priv->cs].chstat) &
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
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(OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
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;
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/* Disable the channel otherwise the next immediate RX will get affected */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
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void *rxp, unsigned long flags)
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{
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int i, chconf;
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ulong start;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/* Enable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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writel(0, &priv->regs->channel[priv->cs].tx);
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for (i = 0; i < len; i++) {
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start = get_timer(0);
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/* Wait till RX register contains data (RXS == 1) */
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Disable the channel to prevent furher receiving */
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if (i == (len - 1))
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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/* Read the data */
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unsigned int *rx = &priv->regs->channel[priv->cs].rx;
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if (priv->wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (priv->wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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/*McSPI Transmit Receive Mode*/
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static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
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const void *txp, void *rxp, unsigned long flags)
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{
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ulong start;
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int chconf, i = 0;
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chconf = readl(&priv->regs->channel[priv->cs].chconf);
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/*Enable SPI channel*/
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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/*set TRANSMIT-RECEIVE Mode*/
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chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
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chconf |= (priv->wordlen - 1) << 7;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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/*Shift in and out 1 byte at time*/
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for (i=0; i < len; i++){
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/* Write: wait for TX empty (TXS == 1)*/
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Write the data */
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unsigned int *tx = &priv->regs->channel[priv->cs].tx;
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if (priv->wordlen > 16)
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writel(((u32 *)txp)[i], tx);
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else if (priv->wordlen > 8)
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writel(((u16 *)txp)[i], tx);
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else
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writel(((u8 *)txp)[i], tx);
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/*Read: wait for RX containing data (RXS == 1)*/
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start = get_timer(0);
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while (!(readl(&priv->regs->channel[priv->cs].chstat) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (get_timer(start) > SPI_WAIT_TIMEOUT) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(&priv->regs->channel[priv->cs].chstat));
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return -1;
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}
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}
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/* Read the data */
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unsigned int *rx = &priv->regs->channel[priv->cs].rx;
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if (priv->wordlen > 16)
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((u32 *)rxp)[i] = readl(rx);
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else if (priv->wordlen > 8)
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((u16 *)rxp)[i] = (u16)readl(rx);
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else
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((u8 *)rxp)[i] = (u8)readl(rx);
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}
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/* Disable the channel */
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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/*if transfer must be terminated disable the channel*/
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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return 0;
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}
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static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int len;
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int ret = -1;
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if (priv->wordlen < 4 || priv->wordlen > 32) {
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printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
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return -1;
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}
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if (bitlen % priv->wordlen)
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return -1;
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len = bitlen / priv->wordlen;
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if (bitlen == 0) { /* only change CS */
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int chconf = readl(&priv->regs->channel[priv->cs].chconf);
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if (flags & SPI_XFER_BEGIN) {
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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omap3_spi_write_chconf(priv, chconf);
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omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
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}
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ret = 0;
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} else {
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if (dout != NULL && din != NULL)
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ret = omap3_spi_txrx(priv, len, dout, din, flags);
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else if (dout != NULL)
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ret = omap3_spi_write(priv, len, dout, flags);
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else if (din != NULL)
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ret = omap3_spi_read(priv, len, din, flags);
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}
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return ret;
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}
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static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
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{
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uint32_t confr, div = 0;
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confr = readl(&priv->regs->channel[priv->cs].chconf);
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/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
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if (priv->freq) {
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while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
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> priv->freq)
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div++;
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} else {
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div = 0xC;
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}
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/* set clock divisor */
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confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
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confr |= div << 2;
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omap3_spi_write_chconf(priv, confr);
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}
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static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
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{
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uint32_t confr;
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confr = readl(&priv->regs->channel[priv->cs].chconf);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
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confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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confr |= OMAP3_MCSPI_CHCONF_DPE0;
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} else {
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confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
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confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
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}
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/* set SPI mode 0..3 */
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confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
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if (priv->mode & SPI_CPHA)
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confr |= OMAP3_MCSPI_CHCONF_PHA;
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if (priv->mode & SPI_CPOL)
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confr |= OMAP3_MCSPI_CHCONF_POL;
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/* set chipselect polarity; manage with FORCE */
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if (!(priv->mode & SPI_CS_HIGH))
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confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
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else
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confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
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/* Transmit & receive mode */
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confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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omap3_spi_write_chconf(priv, confr);
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}
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static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
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{
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unsigned int confr;
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/* McSPI individual channel configuration */
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confr = readl(&priv->regs->channel[priv->cs].chconf);
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/* wordlength */
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confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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confr |= (priv->wordlen - 1) << 7;
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omap3_spi_write_chconf(priv, confr);
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}
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static void spi_reset(struct mcspi *regs)
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{
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unsigned int tmp;
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writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig);
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do {
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tmp = readl(®s->sysstatus);
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} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
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writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig);
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writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable);
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}
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static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
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{
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unsigned int conf;
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/*
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* setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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conf = readl(&priv->regs->modulctrl);
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conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
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conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
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writel(conf, &priv->regs->modulctrl);
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priv->bus_claimed = true;
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}
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static int omap3_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct omap3_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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priv->cs = slave_plat->cs;
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if (!priv->freq)
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priv->freq = slave_plat->max_hz;
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_omap3_spi_claim_bus(priv);
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_omap3_spi_set_speed(priv);
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_omap3_spi_set_mode(priv);
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return 0;
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}
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static int omap3_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct omap3_spi_priv *priv = dev_get_priv(bus);
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writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
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priv->bus_claimed = false;
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return 0;
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}
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static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
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{
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struct udevice *bus = dev->parent;
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struct omap3_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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priv->cs = slave_plat->cs;
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priv->wordlen = wordlen;
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_omap3_spi_set_wordlen(priv);
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return 0;
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}
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static int omap3_spi_probe(struct udevice *dev)
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{
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struct omap3_spi_priv *priv = dev_get_priv(dev);
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struct omap3_spi_plat *plat = dev_get_plat(dev);
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priv->regs = plat->regs;
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priv->pin_dir = plat->pin_dir;
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priv->wordlen = SPI_DEFAULT_WORDLEN;
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spi_reset(priv->regs);
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return 0;
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}
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static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct omap3_spi_priv *priv = dev_get_priv(bus);
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return _spi_xfer(priv, bitlen, dout, din, flags);
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}
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static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
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{
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struct omap3_spi_priv *priv = dev_get_priv(dev);
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priv->freq = speed;
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if (priv->bus_claimed)
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_omap3_spi_set_speed(priv);
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return 0;
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}
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static int omap3_spi_set_mode(struct udevice *dev, uint mode)
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{
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struct omap3_spi_priv *priv = dev_get_priv(dev);
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priv->mode = mode;
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if (priv->bus_claimed)
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_omap3_spi_set_mode(priv);
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return 0;
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}
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static const struct dm_spi_ops omap3_spi_ops = {
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.claim_bus = omap3_spi_claim_bus,
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.release_bus = omap3_spi_release_bus,
|
|
.set_wordlen = omap3_spi_set_wordlen,
|
|
.xfer = omap3_spi_xfer,
|
|
.set_speed = omap3_spi_set_speed,
|
|
.set_mode = omap3_spi_set_mode,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
static struct omap2_mcspi_platform_config omap2_pdata = {
|
|
.regs_offset = 0,
|
|
};
|
|
|
|
static struct omap2_mcspi_platform_config omap4_pdata = {
|
|
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
|
|
};
|
|
|
|
static int omap3_spi_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct omap2_mcspi_platform_config *data =
|
|
(struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
|
|
struct omap3_spi_plat *plat = dev_get_plat(dev);
|
|
|
|
plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
|
|
|
|
if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
|
|
plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
|
else
|
|
plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id omap3_spi_ids[] = {
|
|
{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
|
|
{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
|
|
{ }
|
|
};
|
|
#endif
|
|
U_BOOT_DRIVER(omap3_spi) = {
|
|
.name = "omap3_spi",
|
|
.id = UCLASS_SPI,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
.of_match = omap3_spi_ids,
|
|
.of_to_plat = omap3_spi_of_to_plat,
|
|
.plat_auto = sizeof(struct omap3_spi_plat),
|
|
#endif
|
|
.probe = omap3_spi_probe,
|
|
.ops = &omap3_spi_ops,
|
|
.priv_auto = sizeof(struct omap3_spi_priv),
|
|
};
|