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There are two revisions of unmatched board with different DDR timing, we'd like to support multi-dtb mechanism in SPL, then it selects the right DTB at runtime according to PCB revision in I2C EEPROM. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>