mirror of
https://xff.cz/git/u-boot/
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187 lines
4.2 KiB
C
Executable File
187 lines
4.2 KiB
C
Executable File
/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "usbc_i.h"
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#include <asm/arch/timer.h>
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#include <asm/arch/platform.h>
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/*
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*******************************************************************************
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* usb_open_clock
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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int usb_open_clock(void)
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{
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u32 reg_value = 0;
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#ifdef FPGA_PLATFORM
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//change interfor on fpga
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reg_value = USBC_Readl(SUNXI_SYSCRL_BASE+0x04);
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reg_value |= 0x01;
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USBC_Writel(reg_value,SUNXI_SYSCRL_BASE+0x04);
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#endif
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//Enable module clock for USB phy0
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reg_value = readl(SUNXI_CCM_BASE + 0xcc);
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reg_value |= (1 << 0) | (1 << 8);
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writel(reg_value, (SUNXI_CCM_BASE + 0xcc));
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//delay some time
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__msdelay(10);
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//Gating AHB clock for USB_phy0
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reg_value = readl(SUNXI_CCM_BASE + 0x60);
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reg_value |= (1 << 23);
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writel(reg_value, (SUNXI_CCM_BASE + 0x60));
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//delay to wati SIE stable
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__msdelay(10);
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reg_value = readl(SUNXI_CCM_BASE + 0x2C0);
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reg_value |= (1 << 23);
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writel(reg_value, (SUNXI_CCM_BASE + 0x2C0));
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__msdelay(10);
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reg_value = readl(SUNXI_USBOTG_BASE + 0x420);
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reg_value |= (0x01 << 0);
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writel(reg_value, (SUNXI_USBOTG_BASE + 0x420));
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__msdelay(10);
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reg_value = readl(SUNXI_USBOTG_BASE + 0x410);
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reg_value &= ~(0x01 << 1);
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writel(reg_value, (SUNXI_USBOTG_BASE + 0x410));
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__msdelay(10);
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return 0;
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}
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/*
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*******************************************************************************
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* usb_op_clock
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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int usb_close_clock(void)
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{
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u32 reg_value = 0;
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/* AHB reset */
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reg_value = readl(SUNXI_CCM_BASE + 0x2C0);
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reg_value &= ~(1 << 23);
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writel(reg_value, (SUNXI_CCM_BASE + 0x2C0));
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__msdelay(10);
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//关usb ahb时钟
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reg_value = readl(SUNXI_CCM_BASE + 0x60);
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reg_value &= ~(1 << 23);
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writel(reg_value, (SUNXI_CCM_BASE + 0x60));
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//等sie的时钟变稳
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__msdelay(10);
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//关USB phy时钟
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reg_value = readl(SUNXI_CCM_BASE + 0xcc);
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reg_value &= ~((1 << 0) | (1 << 8));
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writel(reg_value, (SUNXI_CCM_BASE + 0xcc));
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__msdelay(10);
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return 0;
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}
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/*
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*******************************************************************************
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* usb_probe_vbus_type
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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int usb_probe_vbus_type(void)
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{
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__u32 base_reg_val;
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__u32 reg_val = 0;
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__u32 dp, dm = 0;
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__u32 dpdm_det[6];
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__u32 dpdm_ret = 0;
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int i =0 ;
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reg_val = readl(SUNXI_USBOTG_BASE + USBC_REG_o_ISCR);
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base_reg_val = reg_val;
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reg_val |= (1 << 16) | (1 << 17);
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writel(reg_val, SUNXI_USBOTG_BASE + USBC_REG_o_ISCR);
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__msdelay(2);
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for(i=0;i<6;i++)
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{
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reg_val = readl(SUNXI_USBOTG_BASE + USBC_REG_o_ISCR);
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dp = (reg_val >> 26) & 0x01;
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dm = (reg_val >> 27) & 0x01;
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dpdm_det[i] = (dp << 1) | dm;
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dpdm_ret += dpdm_det[i];
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__msdelay(1);
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}
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writel(base_reg_val, SUNXI_USBOTG_BASE + USBC_REG_o_ISCR);
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if(dpdm_ret > 12)
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{
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return 1; //DC
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}
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else
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{
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return 0; //PC
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}
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}
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