mirror of
https://xff.cz/git/u-boot/
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129 lines
2.3 KiB
C
Executable File
129 lines
2.3 KiB
C
Executable File
/*
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* (C) Copyright 2013-2016
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "common.h"
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#include "asm/io.h"
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#include "asm/arch/ccmu.h"
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#include "asm/arch/ss.h"
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static int ss_base_mode = 0;
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__weak int ss_get_ver(void)
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{
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#ifdef SS_VER
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/* CE 2.0 */
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u8 val = (readl(SS_VER)>>8) & 0xf;
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return val;
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#else
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return 0;
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#endif
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}
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__weak void ss_set_drq(u32 addr)
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{
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writel(addr, SS_TDQ);
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}
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__weak void ss_ctrl_start(u8 alg_type)
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{
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if(ss_get_ver() == 2)
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{
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/* CE 2.0 */
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writel(alg_type<<8, SS_TLR);
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}
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writel(readl(SS_TLR)|0x1, SS_TLR);
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}
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__weak void ss_ctrl_stop(void)
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{
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writel(0x0, SS_TLR);
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}
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__weak void ss_wait_finish(u32 task_id)
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{
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uint int_en;
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int_en = readl(SS_ICR) & 0xf;
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int_en = int_en&(0x01<<task_id);
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if(int_en!=0)
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{
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while((readl(SS_ISR)&(0x01<<task_id))==0) {};
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}
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}
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__weak void ss_pending_clear(u32 task_id)
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{
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u32 reg_val;
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reg_val = readl(SS_ISR);
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if((reg_val&(0x01<<task_id))==(0x01<<task_id))
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{
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reg_val &= ~(0x0f);
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reg_val |= (0x01<<task_id);
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}
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writel(reg_val, SS_ISR);
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}
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__weak void ss_irq_enable(u32 task_id)
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{
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int val = readl(SS_ICR);
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val |= (0x1<<task_id);
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writel(val, SS_ICR);
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}
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__weak void ss_irq_disable(u32 task_id)
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{
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int val = readl(SS_ICR);
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val &= ~(1 << task_id);
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writel(val, SS_ICR);
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}
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__weak u32 ss_check_err(void)
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{
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return (readl(SS_ERR) & 0xffff);
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}
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__weak void ss_open(void)
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{
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u32 reg_val;
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reg_val = readl(CCMU_CE_CLK_REG);
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/*set CE src clock*/
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reg_val &= ~(CE_CLK_SRC_MASK<<CE_CLK_SRC_SEL_BIT);
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reg_val |= CE_CLK_SRC<<CE_CLK_SRC_SEL_BIT;
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/*set div n*/
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reg_val &= ~(CE_CLK_DIV_RATION_N_MASK<<CE_CLK_DIV_RATION_N_BIT);
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reg_val |= CE_CLK_DIV_RATION_N<<CE_CLK_DIV_RATION_N_BIT;
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/*set div m*/
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reg_val &= ~(CE_CLK_DIV_RATION_M_MASK<<CE_CLK_DIV_RATION_M_BIT);
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reg_val |= CE_CLK_DIV_RATION_M<<CE_CLK_DIV_RATION_M_BIT;
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/*set src clock on*/
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reg_val |= CE_SCLK_ON<<CE_SCLK_ONOFF_BIT;
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writel(reg_val,CCMU_CE_CLK_REG);
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/*open CE gating*/
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reg_val = readl(CE_GATING_BASE);
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reg_val |= CE_GATING_PASS<<CE_GATING_BIT;
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writel(reg_val,CE_GATING_BASE);
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/*assert*/
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reg_val = readl(CE_RST_REG_BASE);
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reg_val &= ~(CE_DEASSERT<<CE_RST_BIT);
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writel(reg_val,CE_RST_REG_BASE);
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/*de-assert*/
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reg_val = readl(CE_RST_REG_BASE);
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reg_val |= CE_DEASSERT<<CE_RST_BIT;
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writel(reg_val,CE_RST_REG_BASE);
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}
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__weak void ss_close(void)
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{
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}
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