mirror of
https://xff.cz/git/u-boot/
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491 lines
11 KiB
C
Executable File
491 lines
11 KiB
C
Executable File
/*
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* (C) Copyright 2017-2020
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*Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*zhouhuacai <zhouhuacai@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/spi.h>
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#include <asm/arch/ccmu.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/clock.h>
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#include <sys_config.h>
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#include <sys_config_old.h>
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#define USE_DMA
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//#define SUNXI_NOR_FLASH_DEBUG 1
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#ifdef SUNXI_NOR_FLASH_DEBUG
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#define SUNXI_DEBUG(fmt,args...) printf(fmt ,##args)
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#else
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#define SUNXI_DEBUG(fmt,args...) do {} while(0)
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#endif
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static u32 g_cfg_mclk = 0;
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static sunxi_dma_setting_t *spi_tx_dma;
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static sunxi_dma_setting_t *spi_rx_dma;
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static uint spi_tx_dma_hd;
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static uint spi_rx_dma_hd;
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#ifdef USE_DMA
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static int spi_dma_recv_start(uint spi_no, uchar* pbuf, uint byte_cnt)
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{
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flush_cache((uint)pbuf, byte_cnt);
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sunxi_dma_start(spi_rx_dma_hd, SPI_RXD, (uint)pbuf, byte_cnt);
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return 0;
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}
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static int spi_wait_dma_recv_over(uint spi_no)
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{
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return sunxi_dma_querystatus(spi_rx_dma_hd);
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}
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static int spi_dma_send_start(uint spi_no, uchar* pbuf, uint byte_cnt)
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{
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flush_cache((uint)pbuf, byte_cnt);
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sunxi_dma_start(spi_tx_dma_hd, (uint)pbuf, SPI_TXD, byte_cnt);
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return 0;
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}
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static int spi_wait_dma_send_over(uint spi_no)
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{
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return sunxi_dma_querystatus(spi_tx_dma_hd);
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}
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#endif
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static u32 spi_cfg_mclk(u32 spi_no, u32 src, u32 mclk)
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{
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u32 mclk_base = CCMU_SPI0_SCLK_CTRL;
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u32 source_clk = 0;
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u32 rval;
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u32 m, n, div;
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switch (src) {
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case 0:
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source_clk = 24000000;
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break;
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case 1:
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source_clk = ccm_get_pll_periph_clk() * 1000000;
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break;
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default :
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SUNXI_DEBUG("Wrong SPI clock source :%x\n", src);
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}
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SUNXI_DEBUG("SPI clock source :0x%x\n", source_clk);
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if (!src) {
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rval = (1U << 31);
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writel(rval, mclk_base);
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g_cfg_mclk = source_clk;
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return g_cfg_mclk;
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}
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div = (source_clk + mclk - 1) / mclk;
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div = div == 0 ? 1 : div;
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if (div > 128) {
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m = 2;
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n = 0;
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SUNXI_DEBUG("Source clock is too high\n");
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} else if (div > 64) {
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n = 3;
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m = div >> 3;
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} else if (div > 32) {
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n = 2;
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m = div >> 2;
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} else if (div > 16) {
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n = 1;
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m = div >> 1;
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} else {
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n = 0;
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m = div;
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}
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rval = (1U << 31) | (src << 24) | (n << 16) | (m - 1);
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writel(rval, mclk_base);
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g_cfg_mclk = source_clk / (1 << n) / (m - 1);
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SUNXI_DEBUG("spi spic->sclk =0x%x\n", g_cfg_mclk );
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return g_cfg_mclk;
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}
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static u32 spi_get_mlk(u32 spi_no)
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{
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#ifdef CONFIG_ARCH_SUN3IW1P1
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/*for sun3i, mclk of spi is ahb clk*/
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return sunxi_clock_get_ahb() * 1000000;
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#else
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return g_cfg_mclk ;
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#endif
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}
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static int spi_gpio_cfg(int spi_no)
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{
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int ret = -1;
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ret = gpio_request_simple("spi0", NULL);
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if (ret)
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printf("\n error:fail to set the spi gpio\n");
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return ret;
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}
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static void spi_onoff(u32 spi_no, u32 onoff)
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{
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u32 clkid[] = {SPI0_CKID, SPI1_CKID, SPI2_CKID, SPI3_CKID};
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switch (spi_no) {
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case 0:
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spi_gpio_cfg(0);
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break;
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default:
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break;
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}
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ccm_module_reset(clkid[spi_no]);
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if (onoff)
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ccm_clock_enable(clkid[spi_no]);
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else
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ccm_clock_disable(clkid[spi_no]);
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}
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static void spic_set_clk(u32 spi_no, u32 clk)
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{
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u32 mclk = spi_get_mlk(spi_no);
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u32 div;
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u32 cdr1 = 0;
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u32 cdr2 = 0;
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u32 cdr_sel = 0;
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div = mclk / (clk << 1);
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if (div == 0) {
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cdr1 = 0;
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cdr2 = 0;
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cdr_sel = 0;
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} else if (div <= 0x100) {
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cdr1 = 0;
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cdr2 = div - 1;
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cdr_sel = 1;
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} else {
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div = 0;
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while (mclk > clk) {
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div++;
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mclk >>= 1;
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}
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cdr1 = div;
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cdr2 = 0;
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cdr_sel = 0;
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}
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writel((cdr_sel << 12) | (cdr1 << 8) | cdr2, SPI_CCR);
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SUNXI_DEBUG("spic_set_clk:mclk=0x%x\n", mclk);
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}
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static int spi_dma_cfg(u32 spi_no)
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{
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spi_rx_dma = malloc_noncache(sizeof(sunxi_dma_setting_t));
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spi_tx_dma = malloc_noncache(sizeof(sunxi_dma_setting_t));
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if (!(spi_rx_dma) || !(spi_tx_dma)) {
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printf("no enough memory to malloc \n");
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return -1;
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}
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memset(spi_tx_dma , 0 , sizeof(sunxi_dma_setting_t));
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memset(spi_rx_dma , 0 , sizeof(sunxi_dma_setting_t));
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spi_rx_dma_hd = sunxi_dma_request(DMAC_DMATYPE_NORMAL);
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spi_tx_dma_hd = sunxi_dma_request(DMAC_DMATYPE_NORMAL);
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if ((spi_tx_dma_hd == 0) || (spi_rx_dma_hd == 0)) {
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printf("spi request dma failed\n");
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return -1;
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}
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//config spi rx dma
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spi_rx_dma->loop_mode = 0;
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spi_rx_dma->wait_cyc = 0x20;
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//spi_rx_dma->data_block_size = 1 * DMAC_CFG_SRC_DATA_WIDTH_8BIT/8;
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spi_rx_dma->data_block_size = 1 * 32 / 8;
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spi_rx_dma->cfg.src_drq_type = DMAC_CFG_TYPE_SPI0; //SPI0
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spi_rx_dma->cfg.src_addr_mode = DMAC_CFG_SRC_ADDR_TYPE_IO_MODE;
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spi_rx_dma->cfg.src_burst_length = DMAC_CFG_SRC_1_BURST;
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spi_rx_dma->cfg.src_data_width = DMAC_CFG_SRC_DATA_WIDTH_32BIT;
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spi_rx_dma->cfg.dst_drq_type = DMAC_CFG_TYPE_DRAM; //DRAM
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spi_rx_dma->cfg.dst_addr_mode = DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE;
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spi_rx_dma->cfg.dst_burst_length = DMAC_CFG_DEST_1_BURST;
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spi_rx_dma->cfg.dst_data_width = DMAC_CFG_DEST_DATA_WIDTH_32BIT;
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spi_tx_dma->loop_mode = 0;
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spi_tx_dma->wait_cyc = 0x20;
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//spi_tx_dma->data_block_size = 1 * DMAC_CFG_SRC_DATA_WIDTH_8BIT/8;
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spi_tx_dma->data_block_size = 1 * 32 / 8;
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spi_tx_dma->cfg.src_drq_type = DMAC_CFG_TYPE_DRAM; //
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spi_tx_dma->cfg.src_addr_mode = DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE;
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spi_tx_dma->cfg.src_burst_length = DMAC_CFG_SRC_1_BURST;
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spi_tx_dma->cfg.src_data_width = DMAC_CFG_SRC_DATA_WIDTH_32BIT;
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spi_tx_dma->cfg.dst_drq_type = DMAC_CFG_TYPE_SPI0; //SPI0
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spi_tx_dma->cfg.dst_addr_mode = DMAC_CFG_DEST_ADDR_TYPE_IO_MODE;
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spi_tx_dma->cfg.dst_burst_length = DMAC_CFG_DEST_1_BURST;
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spi_tx_dma->cfg.dst_data_width = DMAC_CFG_DEST_DATA_WIDTH_32BIT;
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//spi_tx_dma->wait_cyc = 0x10;
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return 0;
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}
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static void sunxi_dma_isr(void *p_arg)
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{
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// printf("dma int occur\n");
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}
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int spic_init(u32 spi_no)
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{
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u32 rval;
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int ret;
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u32 spi_clck;
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if (spi_dma_cfg(spi_no)) {
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printf("spi dma cfg error!\n");
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return -1;
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}
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sunxi_dma_install_int(spi_rx_dma_hd, sunxi_dma_isr, NULL);
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sunxi_dma_install_int(spi_tx_dma_hd, sunxi_dma_isr, NULL);
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sunxi_dma_enable_int(spi_rx_dma_hd);
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sunxi_dma_enable_int(spi_tx_dma_hd);
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sunxi_dma_setting(spi_rx_dma_hd, (void *)spi_rx_dma);
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sunxi_dma_setting(spi_tx_dma_hd, (void *)spi_tx_dma);
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spi_onoff(spi_no, 1);
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#ifndef CONFIG_ARCH_SUN3IW1P1
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spi_cfg_mclk(spi_no, 1, SPI_MCLK);
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#endif
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#ifdef FPGA_PLATFORM
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//24M
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spi_cfg_mclk(spi_no, 0, SPI_MCLK);
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#else
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//pll6
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spi_cfg_mclk(spi_no, 1, SPI_MCLK);
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#endif
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ret = script_parser_fetch("boot_spi_board0", "boot_spi_speed_hz", (int *)(&spi_clck),1);
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if (ret < 0)
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{
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spic_set_clk(spi_no, SPI_DEFAULT_CLK);
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}
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else
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{
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spic_set_clk(spi_no, spi_clck);
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}
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rval = SPI_SOFT_RST | SPI_TXPAUSE_EN | SPI_MASTER | SPI_ENABLE;
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writel(rval, SPI_GCR);
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rval = SPI_SET_SS_1 | SPI_DHB | SPI_SS_ACTIVE0; //set ss to high,discard unused burst,SPI select signal polarity(low,1=idle)
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writel(rval, SPI_TCR);
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writel(SPI_TXFIFO_RST | (SPI_TX_WL << 16) | (SPI_RX_WL), SPI_FCR);
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return 0;
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}
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#ifdef USE_DMA
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int spic_rw( u32 tcnt, void* txbuf, u32 rcnt, void* rxbuf)
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{
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u32 i = 0, fcr, ier;
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int timeout = 0xfffff;
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u8 *tx_buffer = txbuf ;
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u8 *rx_buffer = rxbuf;
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writel(0, SPI_IER);
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writel(0xffffffff, SPI_ISR );//clear status register
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ier = readl(SPI_IER)|SPI_TC_INT; //transmit complete enable
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writel(ier, SPI_IER);
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writel(tcnt, SPI_MTC);
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writel(tcnt + rcnt, SPI_MBC);
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writel(readl(SPI_TCR) | SPI_EXCHANGE, SPI_TCR);
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/* start transmit */
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timeout = 0xfffff;
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if (tcnt) {
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if (tcnt < 64 ) {
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i = 0;
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while (i < tcnt) {
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//send data
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while (((readl(SPI_FSR) >> 16) == SPI_FIFO_SIZE) );
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writeb(*(tx_buffer + i), SPI_TXD);
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i++;
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}
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} else {
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writel((readl(SPI_FCR) | SPI_TXDMAREQ_EN), SPI_FCR);
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spi_dma_send_start(0, txbuf, tcnt);
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/* wait DMA finish */
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while ((timeout-- > 0) && spi_wait_dma_send_over(0));
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if (timeout <= 0) {
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printf("tx wait_dma_send_over fail\n");
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return -1;
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}
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}
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}
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timeout = 0xfffff;
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if (rcnt) {
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if (rcnt < 64) {
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i = 0;
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while (i < rcnt) {
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//receive valid data
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while (((readl(SPI_FSR))&0x7f) == 0);
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*(rx_buffer + i) = readb(SPI_RXD);
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i++;
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}
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} else {
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timeout = 0xfffff;
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writel((readl(SPI_FCR) | SPI_RXDMAREQ_EN), SPI_FCR);
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spi_dma_recv_start(0, rxbuf, rcnt);
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/* wait DMA finish */
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while ((timeout-- > 0) && spi_wait_dma_recv_over(0));
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if (timeout <= 0) {
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printf("rx wait_dma_recv_over fail\n");
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return -1;
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}
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}
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}
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//check fifo error
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if ((readl(SPI_ISR) & (0xf << 8)))
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return RET_FAIL;
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//check tx/rx finish:fifo<-->nor
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timeout = 0xfffff;
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while (!(readl(SPI_ISR)&(0x1 << 12))) { //wait transfer complete
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timeout--;
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if (!timeout) {
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printf("SPI_ISR time_out \n");
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return RET_FAIL;
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}
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}
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//check dma status
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timeout = 0xfffff;
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while (DMA_CHAN_STA_REG & 0x1) {
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timeout--;
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if (!timeout) {
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printf("DMA_CHAN_STA_REG timeout\n");
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break;
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}
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}
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//disable dma req
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fcr = readl(SPI_FCR);
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fcr &= ~(SPI_TXDMAREQ_EN | SPI_RXDMAREQ_EN);
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writel(fcr, SPI_FCR);
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//check SPI_EXCHANGE when SPI_MBC is 0
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if (readl(SPI_MBC) == 0) {
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if (readl(SPI_TCR)&SPI_EXCHANGE) {
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printf("XCH Control Error!!\n");
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return RET_FAIL;
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}
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} else {
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printf("SPI_MBC Error!\n");
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return RET_FAIL;
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}
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writel(0xfffff, SPI_ISR); /* clear flag */
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return RET_OK;
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}
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#else
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int spic_rw( u32 tcnt, void* txbuf, u32 rcnt, void* rxbuf)
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{
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u32 i = 0;
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int timeout = 0xfffff;
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//uint ret = 0;
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u8 *tx_buffer = txbuf ;
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u8 *rx_buffer = rxbuf;
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writel(0, SPI_IER);
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writel(0xffffffff, SPI_ISR);//clear status register
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writel(tcnt, SPI_MTC);
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writel(tcnt + rcnt, SPI_MBC);
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writel(readl(SPI_TCR) | SPI_EXCHANGE, SPI_TCR);
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if (tcnt) {
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i = 0;
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while (i < tcnt) {
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//send data
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while (((readl(SPI_FSR) >> 16) == SPI_FIFO_SIZE) );
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writeb(*(tx_buffer + i), SPI_TXD);
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i++;
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}
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}
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/* start transmit */
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if (rcnt) {
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i = 0;
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while (i < rcnt) {
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//receive valid data
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while (((readl(SPI_FSR))&0x7f) == 0);
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*(rx_buffer + i) = readb(SPI_RXD);
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i++;
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}
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}
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//check fifo error
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if ((readl(SPI_ISR) & (0xf << 8)))
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return RET_FAIL;
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//check tx/rx finish
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timeout = 0xfffff;
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while (!(readl(SPI_ISR)&(0x1 << 12))) { //wait transfer complete
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timeout--;
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if (!timeout) {
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printf("SPI_ISR time_out \n");
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return RET_FAIL;
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}
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}
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//check SPI_EXCHANGE when SPI_MBC is 0
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if (readl(SPI_MBC) == 0) {
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if (readl(SPI_TCR)&SPI_EXCHANGE) {
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printf("XCH Control Error!!\n");
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return RET_FAIL;
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}
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} else {
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printf("SPI_MBC Error!\n");
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return RET_FAIL;
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}
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writel(0xfffff, SPI_ISR); /* clear flag */
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return RET_OK;
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}
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#endif
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int spic_exit(u32 spi_no)
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{
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if (spi_tx_dma)
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free_noncache(spi_tx_dma);
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if (spi_rx_dma)
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free_noncache(spi_rx_dma);
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sunxi_dma_release(spi_tx_dma_hd);
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sunxi_dma_release(spi_rx_dma_hd);
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return 0;
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}
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void spic_config_dual_mode(u32 spi_no, u32 rxdual, u32 dbc, u32 stc)
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{
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writel((rxdual << 28) | (dbc << 24) | (stc), SPI_BCC);
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}
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